Standard ML of New Jersey
Version 110.14, February 22, 1999

Warning

This version is intended for compiler hackers. We are in the midst of substantial structural changes, and this is a snapshot. It only supports the Sparc, Alpha, HPPA, and PowerPC architectures. Furthermore, there are performance bugs that have to be fixed.

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Summary

This version is intended to introduce the new MLRISC PowerPC code generator, but also includes a few MLRISC bug fixes.

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Bug Fixes

Relative to 110.13

• The alpha (and other architectures) generated LDA and LDAH instructions to load immediate operands where the value was zero (Perry Cheng).

• The register allocator generated an exception for temporaries that were used but not defined. This happens all the time in C (Fermin Reig).

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Features

The cross compilers had no access to the Control structure and could not therefore access flags that affected the cross compilation. Building a cross compiler using CMB.retarget, now defines a structure Compiler as well as CMB. For example, cross compiling to the DEC Alpha will generate Alpha32Compiler and Alpha32UnixCMB. The Alpha32Compiler interface is identical to the Compiler interface, but substructures in Alpha32Compiler are specific to the target being cross compiled to.

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PowerPC notes

The generated code could be improved in a number of ways:

• There are three registers that are wasted. This will be fixed in the next round of runtime system, interface changes.

• Without out-of-order execution, the generated code pays a high penalty for branches. The following sequence is typically generated:

	mtlr	r
	blr	

or

	cmp	cr, r1, r2
	bt	cr, lab

or

	and.	r1, r2, r3
	bt	cr0, lab

In all cases, scheduling the assignment of the link register or the setting of the condition code register far away from the branch would improve the situation dramatically. Various possibilities for accomplishing this are being investigated.

Lal George

Last modified: Mon Mar 22 16:28:20 EST 1999