Standard ML of New Jersey
Version 110.19, July 8, 1999

Warning

This version is intended for compiler hackers. We are in the midst of substantial structural changes, and this is a snapshot.

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Summary:

This version has a large number of MLRISC changes done primarily by Allen Leung. Salient features are:

• MLTree: All operations are explicitly typed by the data width, allowing better support for 16/64 bit operations (or any other width).
• Register encodings: All physical registers are encoded uniquely.
• Machine Descriptions: Nearly all the target specific MLRISC files are now generated from a machine description.
• Annotations: Target machine instructions can be marked with client specific annotations.
• Regions: There is a new way to describing memory aliasing.
• Multiplication/division: There is better support for generating code involving constant operands.
• Documentation: Is in progress but not ready for prime time.
• Execution time improves.

Other Changes include:

• alpha32x is no longer supported.
• changes to support sockets under win32.

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MLRISC Changes

MLTree

• All operators in MLTREE are now typed by the data width. For example, previously to compute x := y + 1 we would write:

                  MV(x,ADD(REG y,LI 1)) 
  	

  Now we write:

              MV(x, 32, ADD(32, REG(32, y), LI 1))
  	

  instead (assuming that x and y are both 32-bit quantities.) To translate old MLTREE to new MLTREE should be a straight forward process.
• There is a larger set of operators. Also, some of the operation names have been changed. For example, we had:

              LOAD32 of rexp * region
  	

  Now, we have

              LOAD of ty * rexp * region
  	

  instead. The ty (data width) parameter specifies the width of the data to be loaded.
• New integer operators are:

            MULS   of ty * rexp * rexp (* signed multiplication/division *)
            DIVS   of ty * rexp * rexp
            REMS   of ty * rexp * rexp
            REMU   of ty * rexp * rexp (* unsigned remainder *)
            NOTB   of ty * rexp        (* ones complement *) 
            CVTI2I of ty * ext * rexp  (* type promotion and conversion *)
            CVTF2I of ty * rounding_mode * fexp
  
             (* 
              * COND(ty,cc,e1,e2):
              * Evaluate into either e1 or e2, depending on cc.  
              * Both e1 and e2 can be evaluated eagerly.
              *)
            COND of ty * ccexp * rexp * rexp
            LOAD_UNALIGNED of ty * rexp * Region.region (* unaligned load *)
            MARK of rexp * Annotations.annotation
           

• New floating-point operators are:

            FLOAD_UNALIGNED  of fty * rexp * Region.region
            FABS of fty * fexp
            FNEG of fty * fexp
            FSQRT of fty * fexp
            CVTI2F of fty * ext * rexp
            CVTF2F of fty * rounding_mode * fexp
            FMARK of fexp * Annotations.annotation
  	  

• Note: not all the new operators have been implemented.
• Order of evaluation:

  	   datatype order = 
  		RL (* right-to-left *) | LR (* left-to-right *)
  	   

  has been removed from arithmetic operators. Where order of evaluation is important, it should be made explicit by sequentially assigning values to temporary registers.

Register encodings

EXTREMELY IMPORTANT: The encoding of physical registers has been changed. All physical registers are now encoded uniquely. For example, on the Sparc, %g0 is encoding as 0 and %f0 is encoding as 32. Previously %f0 was encoded as 0. An MLRISC client should use the function Reg provided by the CELLS interface to compute these new encoding.

	   val Reg : cellkind -> int -> register
      

For example, to describe %f0, use

	  SparcCells.Reg SparcCells.FP 0
      

Annotations

There is a new mechanism to inject client-defined annotations into the program. Annotations can be attached to instructions, basic blocks, control flow edges or an entire cluster/CFG.

These MLTREE constructors:

• MARK of rexp * Annotations.annotation
• FMARK of fexp * Annotations.annotation
• CCMARK of ccexp * Annotations.annotation

inject instruction level annotations. (See MLRISC/instructions/insnProps.sig)

The term

	 BLOCK_ANNOTATION of Annotations.annotation
	

inject a basic block level annotation.

Finally,

	 ENDCLUSTER of int Intmap.intmap * Annotations.annotations
	 

can be used to attach a list of cluster level annotations.

Certain annotations are interpreted specially by the MLRISC system. For example, there is an annotation that specifies branch probability, another that specifies control-dependence etc. (See MLRISC/instructions/basicAnnotations.sig). Annotations are not restricted to the ones that we have predefined; an MLRISC client can freely define its own annotations (annotations are just ML exceptions). Client-defined annotations are propagated and are semantically null -- unless you write a new optimization phase to recognize a new annotation.

Execution time

Compilation and execution time on the HPPA, which has been the most finely tuned architecture in this release, improves from 0-20% depending on the benchmark. Your mileage with other architectures will vary, however, their fine tuning has been deferred to the next version. All other architecture should eventually improve, as a result of the generic multiplication/division by constants, and strength reduction. Currently 110.19 is 6% slower at compiling the compiler than 110.18 on the DEC Alpha.

Machine Descriptions

Nearly all the target specific MLRISC files are generated from a machine description. (See MLRISC/[arch]/[arch].md, where [arch] is one of sparc, hppa, alpha, ppc, or x86). This borrows several ideas from the New Jersey Machine Code Toolkit, and others. The files that process the machine descriptions have not been included in this release.

Regions

Please see the files aliasing/mlriscRegion.{sig,sml} for details.

Multiplication/Division

Strength reduction is performed for integer multiplications and divisions by constants (except on the x86 platform). This almost always leads to faster code. The algorithm that we currently use for strength reduction is very simple; more improvements are possible.

Documentation

Preliminary documentation is included in this version, but is not ready for prime time use. It can be accessed by pointing to . This documentation will be continually updated, and the following page should be used for the latest documentation:

	/cm/cs/what/smlnj/MLRISC
	

See Also

For architecture specific changes, please see the files MLRISC/[arch]/README.[arch] where [arch] is the name of the architecture. For detailed changes to MLRISC, please see the files MLRISC/README and MLRISC/CHANGES.

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Other Changes

Alpha32x

The DEC Alpha under OSF 3.2 is no longer supported. A special code generator was required for this because the OS would not emulate certain floating point instructions. For example, for floating point subtraction, FSUB with the /SUD extension is generated. (/SUD for software completion, underflow enabled, and dynamic rounding mode). Instead OSF 3.2 would generate an illegal instruction error.

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Lal George

Last modified: Mon Jul 12 16:01:06 EDT 1999