Optimizing Circuit Pack Soldering Processes

Optimizing Circuit Pack Soldering Processes

Don Sun, Jim Landwehr, and Scott Vander Wiel

Importance

Soldering very small components onto circuit packs is a crucial step in the assembly of modern electronic equipment, ranging for example from small wireless telephones to large central office switching systems. As automated soldering technology and equipment advances, the challenge remains to develop processes that reliably solder ever-smaller components (say, 20 mil pitch or less) at ever-lower defect rates (say, 10 defects per million joints or less). These problems are being addressed by teams of ERC engineers as part of the design and implementation of the ``Wireless Technology and Production Center (WTPC),'' which is a small, flexible manufacturing facility for wireless telephones being built in Piscataway, NJ.

Description

Careful, iterative experimentation is one important component of developing and optimizing the soldering processes. This involves statistical issues both of experimental design and data analysis. The needs are to quickly and efficiently analyze the results and plan for possible further experiments.

It is very difficult to run experiments to estimate such a low defect rate since the number of solder joints required is huge. Even larger sample sizes are required to reliably detect differences in defect rates corresponding to two experimental conditions (say, solder paste temperature A vs. solder paste temperature B) when the expected defect rates are so low. Therefore, some alternative characteristics that are likely to be correlated with the defect rate need to be investigated in addition to the actual defect rates.

One major component in the process is the volume of solder paste that is applied to bare ("dry") circuit board before surface mounting of the IC chips and discrete components. It is believed by the industry that larger variation in the solder paste volume should cause more defective joints. Thus, an important problem is to identify factors that contribute to the variation of the solder paste volume and to find operating conditions that give low variability. A large amount of solder volume data can be collected automatically by a computer vision system. A series of experiments was conducted in the Piscataway WTPC to achieve the following goals:

1) Understand effects of different circuit board holders on paste volume.
2) Compare different printers in order to purchase the best one.
3) Identify optimal parameter settings of the printer to achieve minimal variation of the paste volume.
4) Relate opens to coplanarity of the leads on an IC and amount of solder paste on the pads of a circuit board.
5) Relate bridges to the amount of solder paste on the pads of a circuit board.
6) Determine operating control limits on the computer visual measurements of the amount of solder paste and on the IC coplanarity specifications so as to produce circuit boards with sufficiently low defect rates.

Methodology

The commonly used fractional factorial designs and mixed-level orthogonal arrays have been used for most of the experiments. Analysis of variance is the main statistical method for identifying significant factors and for decomposing paste volume into its variance components. Some graphical tools that we have developed in the past year have provided very effective ways of communicating the analysis results to the engineers.

Here is an example of a trellis display of the interaction effect between factors IC Site and Printer Holder Rotation from the analysis of one printing experiment:

Illustration of interaction plot

The plot shows that the influence of Site on solder paste Volume has different patterns as the Rotation of the holder changes.

Another useful graphical method is to plot the location of the opens or bridges on all the ICs on each board. Here are two examples displaying open joints and bridges on a circuit board.

Illustration of board plot

Illustration of board plot

One important statistical issue is analyzing the temporal variation of the solder paste volume from board to board. The times since the last stencil wipe and the last addition of solder paste are very important factors influencing paste volume.

Business Unit Interactions

Earl Lory, John Sohn, and Peter Read at ERC are the key collaborators for the project involving the Piscataway WTPC.

An experiment involving surface mount soldering of very small discrete components was run in Columbus in mid-1996. We analyzed the results and had been involved earlier in the design issues. The experiment identified certain pad shapes that are preferable and established dimensions and component spacing smaller than those currently in use for which the process can still perform reliably. The contact was Fred Verdi of ERC.

Status

A series of experiments have been run to achieve the previously stated goals. These experiments helped the engineers choose the appropriate equipment and suppliers and find optimal process parameters. A final experiment introducing some extra variations on solder paste volume and IC coplanarity has been run so as to introduce more defects and thereby better determine the operational window of these two important process variables. The results of all these experiments are being summarized and handed over to the WTPC for engineering builds and production.


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Last modified: $Date: 2000/11/02 21:14:29 $

dxsun@research.bell-labs.com