<AVRPART><MODULE_LIST>[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:POWER:PROGVOLT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS:LOCKBIT]</MODULE_LIST><ADMIN>
<PART_NAME>ATmega163</PART_NAME>
<SPEED>8MHZ</SPEED>
<BUILD>186</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$94</ADDR001>
<ADDR002>$02</ADDR002>
</SIGNATURE>
</ADMIN>
<CORE>
<CORE_VERSION>V2E</CORE_VERSION>
<ID>AVRSimCoreV2.SimCoreV2</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>18</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Reset, Power-on Reset and Watchdog Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt 0</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt 1</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>TIMER2_COMP</SOURCE>
<DEFINITION>Timer/Counter2 Compare Match</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>TIMER2_OVF</SOURCE>
<DEFINITION>Timer/Counter2 Overflow</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>TIMER1_CAPT</SOURCE>
<DEFINITION>Timer/Counter1 Capture Event</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPA</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match A</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$00E</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPB</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match B</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$010</PROGRAM_ADDRESS>
<SOURCE>TIMER1_OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$012</PROGRAM_ADDRESS>
<SOURCE>TIMER0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$014</PROGRAM_ADDRESS>
<SOURCE>SPI,STC</SOURCE>
<DEFINITION>SPI Serial Transfer Complete</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$016</PROGRAM_ADDRESS>
<SOURCE>UART,RX</SOURCE>
<DEFINITION>UART, RX Complete</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$018</PROGRAM_ADDRESS>
<SOURCE>UART,UDRE</SOURCE>
<DEFINITION>UART Data Register Empty</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$01A</PROGRAM_ADDRESS>
<SOURCE>UART,TX</SOURCE>
<DEFINITION>UART, TX Complete</DEFINITION>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$01C</PROGRAM_ADDRESS>
<SOURCE>ADC</SOURCE>
<DEFINITION>ADC Conversion Complete</DEFINITION>
</VECTOR15>
<VECTOR16>
<PROGRAM_ADDRESS>$01E</PROGRAM_ADDRESS>
<SOURCE>EE_RDY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR16>
<VECTOR17>
<PROGRAM_ADDRESS>$020</PROGRAM_ADDRESS>
<SOURCE>ANA_COMP</SOURCE>
<DEFINITION>Analog Comparator</DEFINITION>
</VECTOR17>
<VECTOR18>
<PROGRAM_ADDRESS>$022</PROGRAM_ADDRESS>
<SOURCE>TWI</SOURCE>
<DEFINITION>2-Wire Serial Interface</DEFINITION>
</VECTOR18>
</INTERRUPT_VECTOR>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>16384</PROG_FLASH>
<EEPROM>512</EEPROM>
<INT_SRAM>
<SIZE>1024</SIZE>
<START_ADDR>$60</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>0</SIZE>
<START_ADDR>NA</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>NA</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>NA</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$5F</MEM_STOP_ADDR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<SP8_MASK>0x01</SP8_MASK><SP9_MASK>0x02</SP9_MASK><SP10_MASK>0x04</SP10_MASK></SPH>
<SPL>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<GIMSK>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<INT0_MASK>0x40</INT0_MASK><INT1_MASK>0x80</INT1_MASK></GIMSK>
<GIFR>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<INTF0_MASK>0x40</INTF0_MASK><INTF1_MASK>0x80</INTF1_MASK></GIFR>
<TIMSK>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<TOIE0_MASK>0x01</TOIE0_MASK><TOIE1_MASK>0x04</TOIE1_MASK><OCIE1B_MASK>0x08</OCIE1B_MASK><OCIE1A_MASK>0x10</OCIE1A_MASK><TICIE1_MASK>0x20</TICIE1_MASK><TOIE2_MASK>0x40</TOIE2_MASK><OCIE2_MASK>0x80</OCIE2_MASK></TIMSK>
<TIFR>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<TOV0_MASK>0x01</TOV0_MASK><TOV1_MASK>0x04</TOV1_MASK><OCF1B_MASK>0x08</OCF1B_MASK><OCF1A_MASK>0x10</OCF1A_MASK><ICF1_MASK>0x20</ICF1_MASK><TOV2_MASK>0x40</TOV2_MASK><OCF2_MASK>0x80</OCF2_MASK></TIFR>
<SPMCR>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><BLBSET_MASK>0x08</BLBSET_MASK><ASRE_MASK>0x10</ASRE_MASK><ASB_MASK>0x40</ASB_MASK></SPMCR>
<TWCR>
<IO_ADDR>$36</IO_ADDR>
<MEM_ADDR>$56</MEM_ADDR>
<TWIE_MASK>0x01</TWIE_MASK><TWEN_MASK>0x04</TWEN_MASK><TWWC_MASK>0x08</TWWC_MASK><TWSTO_MASK>0x10</TWSTO_MASK><TWSTA_MASK>0x20</TWSTA_MASK><TWEA_MASK>0x40</TWEA_MASK><TWINT_MASK>0x80</TWINT_MASK></TWCR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><SM0_MASK>0x10</SM0_MASK><SM1_MASK>0x20</SM1_MASK><SE_MASK>0x40</SE_MASK></MCUCR>
<MCUSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK></MCUSR>
<TCCR0>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK></TCCR0>
<TCNT0>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<TCNT00_MASK>0x01</TCNT00_MASK><TCNT01_MASK>0x02</TCNT01_MASK><TCNT02_MASK>0x04</TCNT02_MASK><TCNT03_MASK>0x08</TCNT03_MASK><TCNT04_MASK>0x10</TCNT04_MASK><TCNT05_MASK>0x20</TCNT05_MASK><TCNT06_MASK>0x40</TCNT06_MASK><TCNT07_MASK>0x80</TCNT07_MASK></TCNT0>
<OSCCAL>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<CAL0_MASK>0x01</CAL0_MASK><CAL1_MASK>0x02</CAL1_MASK><CAL2_MASK>0x04</CAL2_MASK><CAL3_MASK>0x08</CAL3_MASK><CAL4_MASK>0x10</CAL4_MASK><CAL5_MASK>0x20</CAL5_MASK><CAL6_MASK>0x40</CAL6_MASK><CAL7_MASK>0x80</CAL7_MASK></OSCCAL>
<SFIOR>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<PSR10_MASK>0x01</PSR10_MASK><PSR2_MASK>0x02</PSR2_MASK><PUD_MASK>0x04</PUD_MASK><ACME_MASK>0x08</ACME_MASK></SFIOR>
<TCCR1A>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<PWM10_MASK>0x01</PWM10_MASK><PWM11_MASK>0x02</PWM11_MASK><FOC1B_MASK>0x04</FOC1B_MASK><FOC1A_MASK>0x08</FOC1A_MASK><COM1B0_MASK>0x10</COM1B0_MASK><COM1B1_MASK>0x20</COM1B1_MASK><COM1A0_MASK>0x40</COM1A0_MASK><COM1A1_MASK>0x80</COM1A1_MASK></TCCR1A>
<TCCR1B>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><CTC1_MASK>0x08</CTC1_MASK><ICES1_MASK>0x40</ICES1_MASK><ICNC1_MASK>0x80</ICNC1_MASK></TCCR1B>
<TCNT1H>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<OCR1AH>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1AH>
<OCR1AL>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1AL>
<OCR1BH>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<OCR1BH0_MASK>0x01</OCR1BH0_MASK><OCR1BH1_MASK>0x02</OCR1BH1_MASK><OCR1BH2_MASK>0x04</OCR1BH2_MASK><OCR1BH3_MASK>0x08</OCR1BH3_MASK><OCR1BH4_MASK>0x10</OCR1BH4_MASK><OCR1BH5_MASK>0x20</OCR1BH5_MASK><OCR1BH6_MASK>0x40</OCR1BH6_MASK><OCR1BH7_MASK>0x80</OCR1BH7_MASK></OCR1BH>
<OCR1BL>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<OCR1BL0_MASK>0x01</OCR1BL0_MASK><OCR1BL1_MASK>0x02</OCR1BL1_MASK><OCR1BL2_MASK>0x04</OCR1BL2_MASK><OCR1BL3_MASK>0x08</OCR1BL3_MASK><OCR1BL4_MASK>0x10</OCR1BL4_MASK><OCR1BL5_MASK>0x20</OCR1BL5_MASK><OCR1BL6_MASK>0x40</OCR1BL6_MASK><OCR1BL7_MASK>0x80</OCR1BL7_MASK></OCR1BL>
<ICR1H>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICR1H0_MASK>0x01</ICR1H0_MASK><ICR1H1_MASK>0x02</ICR1H1_MASK><ICR1H2_MASK>0x04</ICR1H2_MASK><ICR1H3_MASK>0x08</ICR1H3_MASK><ICR1H4_MASK>0x10</ICR1H4_MASK><ICR1H5_MASK>0x20</ICR1H5_MASK><ICR1H6_MASK>0x40</ICR1H6_MASK><ICR1H7_MASK>0x80</ICR1H7_MASK></ICR1H>
<ICR1L>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICR1L0_MASK>0x01</ICR1L0_MASK><ICR1L1_MASK>0x02</ICR1L1_MASK><ICR1L2_MASK>0x04</ICR1L2_MASK><ICR1L3_MASK>0x08</ICR1L3_MASK><ICR1L4_MASK>0x10</ICR1L4_MASK><ICR1L5_MASK>0x20</ICR1L5_MASK><ICR1L6_MASK>0x40</ICR1L6_MASK><ICR1L7_MASK>0x80</ICR1L7_MASK></ICR1L>
<TCCR2>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<CS20_MASK>0x01</CS20_MASK><CS21_MASK>0x02</CS21_MASK><CS22_MASK>0x04</CS22_MASK><WGM21_MASK>0x08</WGM21_MASK><COM20_MASK>0x10</COM20_MASK><COM21_MASK>0x20</COM21_MASK><WGM20_MASK>0x40</WGM20_MASK><FOC2_MASK>0x80</FOC2_MASK></TCCR2>
<TCNT2>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<TCNT2-0_MASK>0x01</TCNT2-0_MASK><TCNT2-1_MASK>0x02</TCNT2-1_MASK><TCNT2-2_MASK>0x04</TCNT2-2_MASK><TCNT2-3_MASK>0x08</TCNT2-3_MASK><TCNT2-4_MASK>0x10</TCNT2-4_MASK><TCNT2-5_MASK>0x20</TCNT2-5_MASK><TCNT2-6_MASK>0x40</TCNT2-6_MASK><TCNT2-7_MASK>0x80</TCNT2-7_MASK></TCNT2>
<OCR2>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<OCR2-0_MASK>0x01</OCR2-0_MASK><OCR2-1_MASK>0x02</OCR2-1_MASK><OCR2-2_MASK>0x04</OCR2-2_MASK><OCR2-3_MASK>0x08</OCR2-3_MASK><OCR2-4_MASK>0x10</OCR2-4_MASK><OCR2-5_MASK>0x20</OCR2-5_MASK><OCR2-6_MASK>0x40</OCR2-6_MASK><OCR2-7_MASK>0x80</OCR2-7_MASK></OCR2>
<ASSR>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<TCR2UB_MASK>0x01</TCR2UB_MASK><OCR2UB_MASK>0x02</OCR2UB_MASK><TCN2UB_MASK>0x04</TCN2UB_MASK><AS2_MASK>0x08</AS2_MASK></ASSR>
<WDTCR>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDTOE_MASK>0x10</WDTOE_MASK></WDTCR>
<UBRRHI>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<UBRRHI0_MASK>0x01</UBRRHI0_MASK><UBRRHI1_MASK>0x02</UBRRHI1_MASK><UBRRHI2_MASK>0x04</UBRRHI2_MASK><UBRRHI3_MASK>0x08</UBRRHI3_MASK></UBRRHI>
<EEARH>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK></EEARH>
<EEARL>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEARL>
<EEDR>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEWE_MASK>0x02</EEWE_MASK><EEMWE_MASK>0x04</EEMWE_MASK><EERIE_MASK>0x08</EERIE_MASK></EECR>
<PORTA>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<MASK>$ff</MASK>
<PORTA0_MASK>0x01</PORTA0_MASK><PORTA1_MASK>0x02</PORTA1_MASK><PORTA2_MASK>0x04</PORTA2_MASK><PORTA3_MASK>0x08</PORTA3_MASK><PORTA4_MASK>0x10</PORTA4_MASK><PORTA5_MASK>0x20</PORTA5_MASK><PORTA6_MASK>0x40</PORTA6_MASK><PORTA7_MASK>0x80</PORTA7_MASK></PORTA>
<DDRA>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<DDA0_MASK>0x01</DDA0_MASK><DDA1_MASK>0x02</DDA1_MASK><DDA2_MASK>0x04</DDA2_MASK><DDA3_MASK>0x08</DDA3_MASK><DDA4_MASK>0x10</DDA4_MASK><DDA5_MASK>0x20</DDA5_MASK><DDA6_MASK>0x40</DDA6_MASK><DDA7_MASK>0x80</DDA7_MASK></DDRA>
<PINA>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<PINA0_MASK>0x01</PINA0_MASK><PINA1_MASK>0x02</PINA1_MASK><PINA2_MASK>0x04</PINA2_MASK><PINA3_MASK>0x08</PINA3_MASK><PINA4_MASK>0x10</PINA4_MASK><PINA5_MASK>0x20</PINA5_MASK><PINA6_MASK>0x40</PINA6_MASK><PINA7_MASK>0x80</PINA7_MASK></PINA>
<PORTB>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<MASK>$ff</MASK>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK><PORTB6_MASK>0x40</PORTB6_MASK><PORTB7_MASK>0x80</PORTB7_MASK></PORTB>
<DDRB>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK><DDB6_MASK>0x40</DDB6_MASK><DDB7_MASK>0x80</DDB7_MASK></DDRB>
<PINB>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK><PINB6_MASK>0x40</PINB6_MASK><PINB7_MASK>0x80</PINB7_MASK></PINB>
<PORTC>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<MASK>$ff</MASK>
<PORTC0_MASK>0x01</PORTC0_MASK><PORTC1_MASK>0x02</PORTC1_MASK><PORTC2_MASK>0x04</PORTC2_MASK><PORTC3_MASK>0x08</PORTC3_MASK><PORTC4_MASK>0x10</PORTC4_MASK><PORTC5_MASK>0x20</PORTC5_MASK><PORTC6_MASK>0x40</PORTC6_MASK><PORTC7_MASK>0x80</PORTC7_MASK></PORTC>
<DDRC>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<DDC0_MASK>0x01</DDC0_MASK><DDC1_MASK>0x02</DDC1_MASK><DDC2_MASK>0x04</DDC2_MASK><DDC3_MASK>0x08</DDC3_MASK><DDC4_MASK>0x10</DDC4_MASK><DDC5_MASK>0x20</DDC5_MASK><DDC6_MASK>0x40</DDC6_MASK><DDC7_MASK>0x80</DDC7_MASK></DDRC>
<PINC>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<PINC0_MASK>0x01</PINC0_MASK><PINC1_MASK>0x02</PINC1_MASK><PINC2_MASK>0x04</PINC2_MASK><PINC3_MASK>0x08</PINC3_MASK><PINC4_MASK>0x10</PINC4_MASK><PINC5_MASK>0x20</PINC5_MASK><PINC6_MASK>0x40</PINC6_MASK><PINC7_MASK>0x80</PINC7_MASK></PINC>
<PORTD>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<MASK>$ff</MASK>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK><PORTD2_MASK>0x04</PORTD2_MASK><PORTD3_MASK>0x08</PORTD3_MASK><PORTD4_MASK>0x10</PORTD4_MASK><PORTD5_MASK>0x20</PORTD5_MASK><PORTD6_MASK>0x40</PORTD6_MASK><PORTD7_MASK>0x80</PORTD7_MASK></PORTD>
<DDRD>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK><DDD2_MASK>0x04</DDD2_MASK><DDD3_MASK>0x08</DDD3_MASK><DDD4_MASK>0x10</DDD4_MASK><DDD5_MASK>0x20</DDD5_MASK><DDD6_MASK>0x40</DDD6_MASK><DDD7_MASK>0x80</DDD7_MASK></DDRD>
<PIND>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK><PIND2_MASK>0x04</PIND2_MASK><PIND3_MASK>0x08</PIND3_MASK><PIND4_MASK>0x10</PIND4_MASK><PIND5_MASK>0x20</PIND5_MASK><PIND6_MASK>0x40</PIND6_MASK><PIND7_MASK>0x80</PIND7_MASK></PIND>
<SPDR>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<SPDR0_MASK>0x01</SPDR0_MASK><SPDR1_MASK>0x02</SPDR1_MASK><SPDR2_MASK>0x04</SPDR2_MASK><SPDR3_MASK>0x08</SPDR3_MASK><SPDR4_MASK>0x10</SPDR4_MASK><SPDR5_MASK>0x20</SPDR5_MASK><SPDR6_MASK>0x40</SPDR6_MASK><SPDR7_MASK>0x80</SPDR7_MASK></SPDR>
<SPSR>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<SPI2X_MASK>0x01</SPI2X_MASK><WCOL_MASK>0x40</WCOL_MASK><SPIF_MASK>0x80</SPIF_MASK></SPSR>
<SPCR>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<SPR0_MASK>0x01</SPR0_MASK><SPR1_MASK>0x02</SPR1_MASK><CPHA_MASK>0x04</CPHA_MASK><CPOL_MASK>0x08</CPOL_MASK><MSTR_MASK>0x10</MSTR_MASK><DORD_MASK>0x20</DORD_MASK><SPE_MASK>0x40</SPE_MASK><SPIE_MASK>0x80</SPIE_MASK></SPCR>
<UDR>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<UDR0_MASK>0x01</UDR0_MASK><UDR1_MASK>0x02</UDR1_MASK><UDR2_MASK>0x04</UDR2_MASK><UDR3_MASK>0x08</UDR3_MASK><UDR4_MASK>0x10</UDR4_MASK><UDR5_MASK>0x20</UDR5_MASK><UDR6_MASK>0x40</UDR6_MASK><UDR7_MASK>0x80</UDR7_MASK></UDR>
<UCSRA>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<MPCM_MASK>0x01</MPCM_MASK><U2X_MASK>0x02</U2X_MASK><OR_MASK>0x08</OR_MASK><FE_MASK>0x10</FE_MASK><UDRE_MASK>0x20</UDRE_MASK><TXC_MASK>0x40</TXC_MASK><RXC_MASK>0x80</RXC_MASK></UCSRA>
<UCSRB>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<TXB8_MASK>0x01</TXB8_MASK><RXB8_MASK>0x02</RXB8_MASK><CHR9_MASK>0x04</CHR9_MASK><TXEN_MASK>0x08</TXEN_MASK><RXEN_MASK>0x10</RXEN_MASK><UDRIE_MASK>0x20</UDRIE_MASK><TXCIE_MASK>0x40</TXCIE_MASK><RXCIE_MASK>0x80</RXCIE_MASK></UCSRB>
<UBRR>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR>
<ACSR>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ACIS0_MASK>0x01</ACIS0_MASK><ACIS1_MASK>0x02</ACIS1_MASK><ACIC_MASK>0x04</ACIC_MASK><ACIE_MASK>0x08</ACIE_MASK><ACI_MASK>0x10</ACI_MASK><ACO_MASK>0x20</ACO_MASK><ACBG_MASK>0x40</ACBG_MASK><ACD_MASK>0x80</ACD_MASK></ACSR>
<ADMUX>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<MUX0_MASK>0x01</MUX0_MASK><MUX1_MASK>0x02</MUX1_MASK><MUX2_MASK>0x04</MUX2_MASK><MUX3_MASK>0x08</MUX3_MASK><MUX4_MASK>0x10</MUX4_MASK><ADLAR_MASK>0x20</ADLAR_MASK><REFS0_MASK>0x40</REFS0_MASK><REFS1_MASK>0x80</REFS1_MASK></ADMUX>
<ADCSR>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ADPS0_MASK>0x01</ADPS0_MASK><ADPS1_MASK>0x02</ADPS1_MASK><ADPS2_MASK>0x04</ADPS2_MASK><ADIE_MASK>0x08</ADIE_MASK><ADIF_MASK>0x10</ADIF_MASK><ADFR_MASK>0x20</ADFR_MASK><ADSC_MASK>0x40</ADSC_MASK><ADEN_MASK>0x80</ADEN_MASK></ADCSR>
<ADCH>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ADCH0_MASK>0x01</ADCH0_MASK><ADCH1_MASK>0x02</ADCH1_MASK><ADCH2_MASK>0x04</ADCH2_MASK><ADCH3_MASK>0x08</ADCH3_MASK><ADCH4_MASK>0x10</ADCH4_MASK><ADCH5_MASK>0x20</ADCH5_MASK><ADCH6_MASK>0x40</ADCH6_MASK><ADCH7_MASK>0x80</ADCH7_MASK></ADCH>
<ADCL>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ADCL0_MASK>0x01</ADCL0_MASK><ADCL1_MASK>0x02</ADCL1_MASK><ADCL2_MASK>0x04</ADCL2_MASK><ADCL3_MASK>0x08</ADCL3_MASK><ADCL4_MASK>0x10</ADCL4_MASK><ADCL5_MASK>0x20</ADCL5_MASK><ADCL6_MASK>0x40</ADCL6_MASK><ADCL7_MASK>0x80</ADCL7_MASK></ADCL>
<TWDR>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<TWD0_MASK>0x01</TWD0_MASK><TWD1_MASK>0x02</TWD1_MASK><TWD2_MASK>0x04</TWD2_MASK><TWD3_MASK>0x08</TWD3_MASK><TWD4_MASK>0x10</TWD4_MASK><TWD5_MASK>0x20</TWD5_MASK><TWD6_MASK>0x40</TWD6_MASK><TWD7_MASK>0x80</TWD7_MASK></TWDR>
<TWAR>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<TWGCE_MASK>0x01</TWGCE_MASK><TWA0_MASK>0x02</TWA0_MASK><TWA1_MASK>0x04</TWA1_MASK><TWA2_MASK>0x08</TWA2_MASK><TWA3_MASK>0x10</TWA3_MASK><TWA4_MASK>0x20</TWA4_MASK><TWA5_MASK>0x40</TWA5_MASK><TWA6_MASK>0x80</TWA6_MASK></TWAR>
<TWSR>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<TWS3_MASK>0x08</TWS3_MASK><TWS4_MASK>0x10</TWS4_MASK><TWS5_MASK>0x20</TWS5_MASK><TWS6_MASK>0x40</TWS6_MASK><TWS7_MASK>0x80</TWS7_MASK></TWSR>
<TWBR>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<TWBR0_MASK>0x01</TWBR0_MASK><TWBR1_MASK>0x02</TWBR1_MASK><TWBR2_MASK>0x04</TWBR2_MASK><TWBR3_MASK>0x08</TWBR3_MASK><TWBR4_MASK>0x10</TWBR4_MASK><TWBR5_MASK>0x20</TWBR5_MASK><TWBR6_MASK>0x40</TWBR6_MASK><TWBR7_MASK>0x80</TWBR7_MASK></TWBR>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>0</NRWW_START_ADDR>
<NRWW_STOP_ADDR>0x1FFF</NRWW_STOP_ADDR>
<RWW_START_ADDR>NA</RWW_START_ADDR>
<RWW_STOP_ADDR>NA</RWW_STOP_ADDR>
<PAGESIZE>64</PAGESIZE>
<BOOTSZMODE1>
<BOOTSIZE>128</BOOTSIZE>
<PAGES>2</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$1F80</BOOTSTART>
<BOOTRESET>$1F80</BOOTRESET>
</BOOTSZMODE1>
<BOOTSZMODE2>
<BOOTSIZE>256</BOOTSIZE>
<PAGES>4</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$1F00</BOOTSTART>
<BOOTRESET>$1F00</BOOTRESET>
</BOOTSZMODE2>
<BOOTSZMODE3>
<BOOTSIZE>512</BOOTSIZE>
<PAGES>8</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$1E00</BOOTSTART>
<BOOTRESET>$1E00</BOOTRESET>
</BOOTSZMODE3>
<BOOTSZMODE4>
<BOOTSIZE>1024</BOOTSIZE>
<PAGES>16</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$1C00</BOOTSTART>
<BOOTRESET>$1C00</BOOTRESET>
</BOOTSZMODE4>
</BOOT_CONFIG>
</MEMORY>
<PACKAGE>
<PACKAGES>[TQFP]</PACKAGES>
<TQFP>
<NMB_PIN>44</NMB_PIN>
<PIN1>
<NAME>[PB5:MOSI]</NAME>
<TEXT>MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</TEXT>
</PIN1>
<PIN2>
<NAME>[PB6:MISO]</NAME>
<TEXT>MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</TEXT>
</PIN2>
<PIN3>
<NAME>[PB7_SCK]</NAME>
<TEXT>SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</TEXT>
</PIN3>
<PIN4>
<NAME>['RESET]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN5>
<PIN6>
<NAME>[GND]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[XTAL2]</NAME>
<TEXT/>
</PIN7>
<PIN8>
<NAME>[XTAL1]</NAME>
<TEXT/>
</PIN8>
<PIN9>
<NAME>[PD0:RXD]</NAME>
<TEXT>Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</TEXT>
</PIN9>
<PIN10>
<NAME>[PD1:TXD]</NAME>
<TEXT>Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</TEXT>
</PIN10>
<PIN11>
<NAME>[PD2:INT0]</NAME>
<TEXT>INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</TEXT>
</PIN11>
<PIN12>
<NAME>[PD3:INT1]</NAME>
<TEXT>INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</TEXT>
</PIN12>
<PIN13>
<NAME>[PD4:OC1B]</NAME>
<TEXT>OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</TEXT>
</PIN13>
<PIN14>
<NAME>[PD5:OC1A]</NAME>
<TEXT>OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</TEXT>
</PIN14>
<PIN15>
<NAME>[PD6:ICP]</NAME>
<TEXT>ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</TEXT>
</PIN15>
<PIN16>
<NAME>[PD7:OC2]</NAME>
<TEXT>OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</TEXT>
</PIN16>
<PIN17>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN17>
<PIN18>
<NAME>[GND]</NAME>
<TEXT/>
</PIN18>
<PIN19>
<NAME>[PC0:SCL]</NAME>
<TEXT>SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal.</TEXT>
</PIN19>
<PIN20>
<NAME>[PC1:SDA]</NAME>
<TEXT>SDA, 2-wire Serial Bus Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is dis-connected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal, and the pin is driven by an open collector driver with slew rate limitation.</TEXT>
</PIN20>
<PIN21>
<NAME>[PC2]</NAME>
<TEXT/>
</PIN21>
<PIN22>
<NAME>[PC3]</NAME>
<TEXT/>
</PIN22>
<PIN23>
<NAME>[PC4]</NAME>
<TEXT/>
</PIN23>
<PIN24>
<NAME>[PC5]</NAME>
<TEXT/>
</PIN24>
<PIN25>
<NAME>[PC6:TOSC1]</NAME>
<TEXT/>
</PIN25>
<PIN26>
<NAME>[PC7:TOSC2]</NAME>
<TEXT/>
</PIN26>
<PIN27>
<NAME>[AVCC]</NAME>
<TEXT/>
</PIN27>
<PIN28>
<NAME>[AGND]</NAME>
<TEXT/>
</PIN28>
<PIN29>
<NAME>[AREF]</NAME>
<TEXT/>
</PIN29>
<PIN30>
<NAME>[PA7:ADC7]</NAME>
<TEXT/>
</PIN30>
<PIN31>
<NAME>[PA6:ADC6]</NAME>
<TEXT/>
</PIN31>
<PIN32>
<NAME>[PA5:ADc5]</NAME>
<TEXT/>
</PIN32>
<PIN33>
<NAME>[PA4:ADC4]</NAME>
<TEXT/>
</PIN33>
<PIN34>
<NAME>[PA3:ADC3]</NAME>
<TEXT/>
</PIN34>
<PIN35>
<NAME>[PA2:ADC2]</NAME>
<TEXT/>
</PIN35>
<PIN36>
<NAME>[PA1:ADC1]</NAME>
<TEXT/>
</PIN36>
<PIN37>
<NAME>[PA0:ADC0]</NAME>
<TEXT/>
</PIN37>
<PIN38>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN38>
<PIN39>
<NAME>[GND]</NAME>
<TEXT/>
</PIN39>
<PIN40>
<NAME>[PB0:T0]</NAME>
<TEXT>T0: Timer/Counter0 counter source. See the timer description for further details.</TEXT>
</PIN40>
<PIN41>
<NAME>[PB1:T1]</NAME>
<TEXT>T1: Timer/Counter1 counter source. See the timer description for further details</TEXT>
</PIN41>
<PIN42>
<NAME>[PB2:AIN0]</NAME>
<TEXT>AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</TEXT>
</PIN42>
<PIN43>
<NAME>[PB3:AIN1]</NAME>
<TEXT>AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</TEXT>
</PIN43>
<PIN44>
<NAME>[PB4:'SS]</NAME>
<TEXT>SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</TEXT>
</PIN44>
</TQFP>
</PACKAGE>
<POWER>
<CLOCK>8MHz</CLOCK>
<TEMP>25C</TEMP>
<ACTIVE>15.0mA</ACTIVE>
<IDLE>8.0mA</IDLE>
<POWER_DOWN><1uA</POWER_DOWN>
</POWER>
<PROGVOLT>
<SER_PROG_MIN_V>4.0</SER_PROG_MIN_V>
<SER_PROG_MAX_V>5.5</SER_PROG_MAX_V>
<PAR_PROG_MIN_V>4.0</PAR_PROG_MIN_V>
<PAR_PROG_MAX_V>5.5</PAR_PROG_MAX_V>
</PROGVOLT>
<FUSE>
<LIST>[LOW:HIGH]</LIST>
<ICON/>
<ID/>
<TEXT/>
<LOW>
<NMB_FUSE_BITS>7</NMB_FUSE_BITS>
<FUSE7>
<NAME>BODLEVEL</NAME>
<TEXT>Brown out detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>BODEN</NAME>
<TEXT>Brown out detector enable</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SPIEN</NAME>
<TEXT>Enable Serial programming and Data Downloading</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE5>
<FUSE3>
<NAME>CKSEL3</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>CKSEL2</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>CKSEL1</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>CKSEL0</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE0>
<NMB_TEXT>20</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Brown-out detection level at VCC=4.0 V</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x80</MASK>
<VALUE>0x80</VALUE>
<TEXT>Brown-out detection level at VCC=2.7 V</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Brown-out detection enabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0F</MASK>
<VALUE>0x00</VALUE>
<TEXT>CKSEL=0000 External Clock fast rising power</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0F</MASK>
<VALUE>0x01</VALUE>
<TEXT>CKSEL=0001 External Clock BOD enabled</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0F</MASK>
<VALUE>0x02</VALUE>
<TEXT>CKSEL=0010 Internal RC Ocsillator slowly rising power ; default value</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x0F</MASK>
<VALUE>0x03</VALUE>
<TEXT>CKSEL=0011 Internal RC Ocsillator fast rising power</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x0F</MASK>
<VALUE>0x04</VALUE>
<TEXT>CKSEL=0100 Internal RC Oscillator BOD enabled</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x0F</MASK>
<VALUE>0x05</VALUE>
<TEXT>CKSEL=0101 External RC Oscillator slowly rising power</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x0F</MASK>
<VALUE>0x06</VALUE>
<TEXT>CKSEL=0110 External RC Oscillator fast rising power</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x0F</MASK>
<VALUE>0x07</VALUE>
<TEXT>CKSEL=0111 External RC Oscillator BOD enabled</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x0F</MASK>
<VALUE>0x08</VALUE>
<TEXT>CKSEL=1000 External Low-Frequency Crystal</TEXT>
</TEXT13>
<TEXT14>
<MASK>0x0F</MASK>
<VALUE>0x09</VALUE>
<TEXT>CKSEL=1001 External Low-Frequency Crystal</TEXT>
</TEXT14>
<TEXT15>
<MASK>0x0F</MASK>
<VALUE>0x0A</VALUE>
<TEXT>CKSEL=1010 Crystal Oscillator slowly rising power</TEXT>
</TEXT15>
<TEXT16>
<MASK>0x0F</MASK>
<VALUE>0x0B</VALUE>
<TEXT>CKSEL=1011 Crystal Oscillator fast rising power</TEXT>
</TEXT16>
<TEXT17>
<MASK>0x0F</MASK>
<VALUE>0x0C</VALUE>
<TEXT>CKSEL=1100 Crystal Oscillator BOD enabled</TEXT>
</TEXT17>
<TEXT18>
<MASK>0x0F</MASK>
<VALUE>0x0D</VALUE>
<TEXT>CKSEL=1101 Ceramic Resonator/External Clock slowly rising power</TEXT>
</TEXT18>
<TEXT19>
<MASK>0x0F</MASK>
<VALUE>0x0E</VALUE>
<TEXT>CKSEL=1110 Ceramic Resonator fast rising power</TEXT>
</TEXT19>
<TEXT20>
<MASK>0x0F</MASK>
<VALUE>0x0F</VALUE>
<TEXT>CKSEL=1111 Ceramic Resonator BOD enabled</TEXT>
</TEXT20>
</LOW>
<HIGH>
<NMB_FUSE_BITS>3</NMB_FUSE_BITS>
<FUSE2>
<NAME>BOOTSZ1</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BOOTSZ0</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>BOOTRST</NAME>
<TEXT>Select Reset Vector</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>5</NMB_TEXT>
<TEXT1>
<MASK>0x06</MASK>
<VALUE>0x06</VALUE>
<TEXT>Boot Flash section size=128 words Boot start address=$1F80 ; default value</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x06</MASK>
<VALUE>0x04</VALUE>
<TEXT>Boot Flash section size=256 words Boot start address=$1F00</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x06</MASK>
<VALUE>0x02</VALUE>
<TEXT>Boot Flash section size=512 words Boot start address=$1E00</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x06</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Flash section size=1024 words Boot start address=$1C00</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Reset vector Enabled (default address=$0000)</TEXT>
</TEXT5>
</HIGH>
</FUSE>
<PROGRAMMING>
<ISPInterface>
<FuseReadMask>0xdf,0xff</FuseReadMask>
<FuseProgMask>0xdf,0xff</FuseProgMask>
<FuseWarning>0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
</ISPInterface>
<HVInterface>
<FuseWarning>0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
</HVInterface>
<OscCal>
<OCEntry>0x00,1.0 MHz</OCEntry>
</OscCal>
<FlashPageSize>128</FlashPageSize>
<EepromPageSize>0</EepromPageSize>
</PROGRAMMING>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_LOCK_BITS>6</NMB_LOCK_BITS>
<NMB_TEXT>11</NMB_TEXT>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0C</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Application Protection Mode 1: No lock on SPM and LPM in Application Section</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0C</MASK>
<VALUE>0x08</VALUE>
<TEXT>Application Protection Mode 2: SPM prohibited in Application Section</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0C</MASK>
<VALUE>0x00</VALUE>
<TEXT>Application Protection Mode 3: LPM and SPM prohibited in Application Section</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0C</MASK>
<VALUE>0x04</VALUE>
<TEXT>Application Protection Mode 4: LPM prohibited in Application Section</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section</TEXT>
</TEXT11>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT1>
<LOCKBIT2>
<NAME>BLB01</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT2>
<LOCKBIT3>
<NAME>BLB02</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT3>
<LOCKBIT4>
<NAME>BLB11</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT4>
<LOCKBIT5>
<NAME>BLB12</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT5>
</LOCKBIT>
<IO_MODULE><MODULE_LIST>[TIMER_COUNTER_0:CPU:TIMER_COUNTER_1:TIMER_COUNTER_2:WATCHDOG:EEPROM:SPI:UART:TWI:PORTA:PORTB:PORTC:PORTD:ANALOG_COMPARATOR:AD_CONVERTER:EXTERNAL_INTERRUPT:BOOT_LOAD]</MODULE_LIST><TIMER_COUNTER_0>
<LIST>[TIMSK:TIFR:TCCR0:TCNT0]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>t81</ID>
<TEXT>The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions</TEXT>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT0>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT0>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT>The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR>
<TCCR0>
<NAME>TCCR0</NAME>
<DESCRIPTION>Timer/Counter0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer Counter 0</DESCRIPTION>
<TEXT>The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.</TEXT>
<IO_ADDR>$32</IO_ADDR>
<MEM_ADDR>$52</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT07</NAME>
<DESCRIPTION>Timer Counter 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT06</NAME>
<DESCRIPTION>Timer Counter 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT05</NAME>
<DESCRIPTION>Timer Counter 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT04</NAME>
<DESCRIPTION>Timer Counter 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT03</NAME>
<DESCRIPTION>Timer Counter 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT02</NAME>
<DESCRIPTION>Timer Counter 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT01</NAME>
<DESCRIPTION>Timer Counter 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT00</NAME>
<DESCRIPTION>Timer Counter 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
</TIMER_COUNTER_0>
<CPU>
<LIST>[SREG:SPH:SPL:OSCCAL:MCUCR:MCUSR:SFIOR]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DESCRIPTION>Sign Bit</DESCRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R</TEXT>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT2>
<NAME>SP10</NAME>
<DESCRIPTION>Stack pointer bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP9</NAME>
<DESCRIPTION>Stack pointer bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack pointer bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt </TEXT>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON>io_spl.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack pointer bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPL>
<OSCCAL>
<NAME>OSCCAL</NAME>
<DESCRIPTION>Oscillator Calibration Value</DESCRIPTION>
<TEXT>Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14</TEXT>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CAL7</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit7</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CAL6</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit6</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CAL5</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CAL4</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CAL3</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CAL2</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CAL1</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CAL0</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OSCCAL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>SE</NAME>
<DESCRIPTION>Sleep enable</DESCRIPTION>
<TEXT>The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SM1</NAME>
<DESCRIPTION>Sleep Mode Select Bit 1</DESCRIPTION>
<TEXT>These bits select between the three available sleep modes, (0:0) = Idle. (0:1) = ADC Noise Reduction. (1:0) = Power-down. (1:1) = Power Save.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep Mode Select Bit 1</DESCRIPTION>
<TEXT>These bits select between the three available sleep modes, (0:0) = Idle. (0:1) = ADC Noise Reduction. (1:0) = Power-down. (1:1) = Power Save.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>Interrupt Sense Control 1 Bit 1</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>Interrupt Sense Control 1 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 1</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>Interrupt Sense Control 0 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-out Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<ALIAS>EXTREF</ALIAS>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on reset flag</DESCRIPTION>
<TEXT>This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
<SFIOR>
<NAME>SFIOR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>ACME</NAME>
<DESCRIPTION>Analog Comparator multiplexer Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is cleared (zero), AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input”</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up Disable</DESCRIPTION>
<TEXT>When this bit is set (one), all pull-ups on all ports are disabled. If the bit is cleared (zero), the pull-ups can be individually enabled as described in the chapter “I/O-Ports”.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PSR2</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter2</DESCRIPTION>
<TEXT>When this bit is set (one) the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode. The bit will remain one until the prescaler has been reset. See “Asynchronous Operation of Timer/Counter2” on page 49 for a detailed descrip-tion of asynchronous operation</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PSR10</NAME>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is set (one) the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hard-ware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SFIOR>
</CPU>
<TIMER_COUNTER_1>
<LIST>[TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm1_04.xml</ID>
<TEXT/>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>TICIE1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCIE1A</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareA Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCIE1B</NAME>
<DESCRIPTION>Timer/Counter1 Output CompareB Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF1</NAME>
<DESCRIPTION>Input Capture Flag 1</DESCRIPTION>
<TEXT>The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCF1A</NAME>
<DESCRIPTION>Output Compare Flag 1A</DESCRIPTION>
<TEXT>The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCF1B</NAME>
<DESCRIPTION>Output Compare Flag 1B</DESCRIPTION>
<TEXT>The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
</TIFR>
<TCCR1A>
<NAME>TCCR1A</NAME>
<DESCRIPTION>Timer/Counter1 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2F</IO_ADDR>
<MEM_ADDR>$4F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM1A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM1A0</NAME>
<DESCRIPTION>Comparet Ouput Mode 1A, bit 0</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1B1</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 1</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1B0</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 0</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>FOC1A</NAME>
<DESCRIPTION>Force Output Compare 1A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mod</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>FOC1B</NAME>
<DESCRIPTION>Force Output Compare 1B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PWM11</NAME>
<DESCRIPTION>Pulse Width Modulator Select Bits</DESCRIPTION>
<TEXT>These bits select PWM operation of Timer/Counter1 (0:0) = PWM Disabled. (0:1) = Timer/Counter1 is an 8-bit PWM. (1:0) = Timer/Counter1 is an a 9-bit PWM. (1:1) = is a 10-bit PWM.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PWM10</NAME>
<DESCRIPTION>Pulse Width Modulator Select Bits</DESCRIPTION>
<TEXT>These bits select PWM operation of Timer/Counter1 (0:0) = PWM Disabled. (0:1) = Timer/Counter1 is an 8-bit PWM. (1:0) = Timer/Counter1 is an a 9-bit PWM. (1:1) = is a 10-bit PWM.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1A>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC1</NAME>
<DESCRIPTION>Input Capture 1 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES1</NAME>
<DESCRIPTION>Input Capture 1 Edge Select</DESCRIPTION>
<TEXT>While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>CTC1</NAME>
<DESCRIPTION>Clear Timer/Counter1 on Compare Match</DESCRIPTION>
<TEXT>When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. When a pres-caling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ...|C-1|C|0|1|... When the prescaler is set to divide by 8, the timer will count like this: ...|C-1,C-1,C-1,C-1,C-1,C-1,C-1,C-1|C,C,C,C,C,C,C,C |0,0,0,0,0,0,0,0|1,1,1,1,1,1,1,1|... In PWM mode, this bit has a different function. If the CTC1 bit is cleared in PWM mode, the Timer/Counter1 acts as an up/down counter. If the CTC1 bit is set (one), the Timer/Counter wraps when it reaches the TOP value. Refer to page 41 for a detailed descriptio</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer/Counter1 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1AH>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AH>
<OCR1AL>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AL>
<OCR1BH>
<NAME>OCR1BH</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro</TEXT>
<IO_ADDR>$29</IO_ADDR>
<MEM_ADDR>$49</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BH7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BH6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BH5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BH4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BH3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BH2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BH1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BH0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BH>
<OCR1BL>
<NAME>OCR1BL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BL>
<ICR1H>
<NAME>ICR1H</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1H7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1H6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1H5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1H4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1H3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1H2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1H1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1H0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1H>
<ICR1L>
<NAME>ICR1L</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1L7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1L6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1L5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1L4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1L3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1L2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1L1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1L0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1L>
</TIMER_COUNTER_1>
<TIMER_COUNTER_2>
<LIST>[TIMSK:TIFR:TCCR2:TCNT2:OCR2:ASSR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>At8pwm2_00</ID>
<TEXT>The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls</TEXT>
<TIMSK>
<NAME>TIMSK</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$39</IO_ADDR>
<MEM_ADDR>$59</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>OCIE2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TOIE2</NAME>
<DESCRIPTION>Timer/Counter2 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</TIMSK>
<TIFR>
<NAME>TIFR</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$38</IO_ADDR>
<MEM_ADDR>$58</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>OCF2</NAME>
<DESCRIPTION>Output Compare Flag 2</DESCRIPTION>
<TEXT>The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TOV2</NAME>
<DESCRIPTION>Timer/Counter2 Overflow Flag</DESCRIPTION>
<TEXT>The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</TIFR>
<TCCR2>
<NAME>TCCR2</NAME>
<DESCRIPTION>Timer/Counter2 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC2</NAME>
<DESCRIPTION>Force Output Compare</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WGM20</NAME>
<ALIAS>PWM2</ALIAS>
<DESCRIPTION>Pulse Width Modulator Enable</DESCRIPTION>
<TEXT>When set (one) this bit enables PWM mode for Timer/Counter2.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM21</NAME>
<DESCRIPTION>Compare Output Mode bit 1</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM20</NAME>
<DESCRIPTION>Compare Output Mode bit 0</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM21</NAME>
<ALIAS>CTC2</ALIAS>
<DESCRIPTION>Clear Timer/Counter2 on Compare Match</DESCRIPTION>
<TEXT>When the CTC2 control bit is set (one), Timer/Counter2 is reset to $00 in the CPU clock cycle following a compare match. If the control bit is cleared, the Timer/Counter2 continues counting and is unaffected by a compare match. When a prescal-ing of 1 is used, and the compare register is set to C, the timer will count as follows if CTC2 is set: ...|C-1|C|0|1|... When the prescaler is set to divide by 8, the timer will count like this: ...|C-1,C-1,C-1,C-1,C-1,C-1,C-1,C-1|C,C,C,C,C,C,C,C |0,0,0,0,0,0,0,0|1,1,1,... In PWM mode, this bit has a different function. If the CTC2 bit is cleared in PWM mode, the Timer/Counter acts as an up/down counter. If the CTC2 bit is set (one), the Timer/Counter wraps when it reaches $FF</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS22</NAME>
<DESCRIPTION>Clock Select bit 2</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS21</NAME>
<DESCRIPTION>Clock Select bit 1</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS20</NAME>
<DESCRIPTION>Clock Select bit 0</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR2>
<TCNT2>
<NAME>TCNT2</NAME>
<DESCRIPTION>Timer/Counter2</DESCRIPTION>
<TEXT>This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation.</TEXT>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT2-7</NAME>
<DESCRIPTION>Timer/Counter 2 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT2-6</NAME>
<DESCRIPTION>Timer/Counter 2 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT2-5</NAME>
<DESCRIPTION>Timer/Counter 2 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT2-4</NAME>
<DESCRIPTION>Timer/Counter 2 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT2-3</NAME>
<DESCRIPTION>Timer/Counter 2 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT2-2</NAME>
<DESCRIPTION>Timer/Counter 2 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT2-1</NAME>
<DESCRIPTION>Timer/Counter 2 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT2-0</NAME>
<DESCRIPTION>Timer/Counter 2 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT2>
<OCR2>
<NAME>OCR2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register</DESCRIPTION>
<TEXT>The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/2 /</TEXT>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2-7</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2-6</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2-5</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2-4</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2-3</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2-2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2-1</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2-0</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2>
<ASSR>
<NAME>ASSR</NAME>
<DESCRIPTION>Asynchronous Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>AS2</NAME>
<DESCRIPTION>Asynchronous Timer/counter2</DESCRIPTION>
<TEXT>When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal oscillator and cannot be used as general I/O pins. When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCN2UB</NAME>
<DESCRIPTION>Timer/Counter2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2UB</NAME>
<DESCRIPTION>Output Compare Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCR2UB</NAME>
<DESCRIPTION>Timer/counter Control Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ASSR>
</TIMER_COUNTER_2>
<WATCHDOG>
<LIST>[WDTCR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCR>
<NAME>WDTCR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>WDTOE</NAME>
<ALIAS>WDDE</ALIAS>
<DESCRIPTION>RW</DESCRIPTION>
<TEXT>This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCR>
</WATCHDOG>
<EEPROM>
<LIST>[EEARH:EEARL:EEDR:EECR]</LIST>
<LINK>[EEARH:EEARL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute</TEXT>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Address Register High Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT>EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMWE</NAME>
<ALIAS>EEWEE</ALIAS>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEWE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
<SPI>
<LIST>[SPDR:SPSR:SPCR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>SPI_01</ID>
<TEXT>The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode</TEXT>
<SPDR>
<NAME>SPDR</NAME>
<DESCRIPTION>SPI Data Register</DESCRIPTION>
<TEXT>The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.</TEXT>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SPDR7</NAME>
<DESCRIPTION>SPI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPDR6</NAME>
<DESCRIPTION>SPI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SPDR5</NAME>
<DESCRIPTION>SPI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SPDR4</NAME>
<DESCRIPTION>SPI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SPDR3</NAME>
<DESCRIPTION>SPI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SPDR2</NAME>
<DESCRIPTION>SPI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPDR1</NAME>
<DESCRIPTION>SPI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPDR0</NAME>
<DESCRIPTION>SPI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPDR>
<SPSR>
<NAME>SPSR</NAME>
<DESCRIPTION>SPI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIF</NAME>
<DESCRIPTION>SPI Interrupt Flag</DESCRIPTION>
<TEXT>When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WCOL</NAME>
<DESCRIPTION>Write Collision Flag</DESCRIPTION>
<TEXT>The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT0>
<NAME>SPI2X</NAME>
<DESCRIPTION>Double SPI Speed Bit</DESCRIPTION>
<TEXT>When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPSR>
<SPCR>
<NAME>SPCR</NAME>
<DESCRIPTION>SPI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIE</NAME>
<DESCRIPTION>SPI Interrupt Enable</DESCRIPTION>
<TEXT>This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPE</NAME>
<DESCRIPTION>SPI Enable</DESCRIPTION>
<TEXT>When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DORD</NAME>
<DESCRIPTION>Data Order</DESCRIPTION>
<TEXT>When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MSTR</NAME>
<DESCRIPTION>Master/Slave Select</DESCRIPTION>
<TEXT>This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPOL</NAME>
<DESCRIPTION>Clock polarity</DESCRIPTION>
<TEXT>When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CPHA</NAME>
<DESCRIPTION>Clock Phase</DESCRIPTION>
<TEXT>Refer to Figure 36 or Figure 37 for the functionality of this bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPR1</NAME>
<DESCRIPTION>SPI Clock Rate Select 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPR0</NAME>
<DESCRIPTION>SPI Clock Rate Select 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPCR>
</SPI>
<UART>
<LIST>[UDR:UCSRA:UCSRB:UBRRHI:UBRR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>Uart_01</ID>
<TEXT>The device features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator Generates any Baud Rate • High Baud Rates at Low XTAL Frequencies • 8 or 9 Bits Data • Noise Filtering • Overrun Detection • Framing Error Detection • False Start Bit Detection • Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete • Multi-processor Communication Mode • Double Speed UART Mode</TEXT>
<UDR>
<NAME>UDR</NAME>
<DESCRIPTION>UART I/O Data Register</DESCRIPTION>
<TEXT>The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.</TEXT>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR7</NAME>
<DESCRIPTION>UART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR6</NAME>
<DESCRIPTION>UART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR5</NAME>
<DESCRIPTION>UART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR4</NAME>
<DESCRIPTION>UART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR3</NAME>
<DESCRIPTION>UART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR2</NAME>
<DESCRIPTION>UART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR1</NAME>
<DESCRIPTION>UART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR0</NAME>
<DESCRIPTION>UART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR>
<UCSRA>
<NAME>UCSRA</NAME>
<DESCRIPTION>UART Control and Status register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC</NAME>
<DESCRIPTION>UART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC</NAME>
<DESCRIPTION>UART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE</NAME>
<DESCRIPTION>UART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OR</NAME>
<DESCRIPTION>Overrun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR is read.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>U2X</NAME>
<DESCRIPTION>Double the UART Transmission Speed</DESCRIPTION>
<TEXT>Setting this bit will reduce the division of the baud rate generator clock from 16 to 8, effectively doubling the transfer speed at the expense of robustness.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM</NAME>
<DESCRIPTION>Multi Processor Communication Mode</DESCRIPTION>
<TEXT>This bit is used to enter Multi-Processor Communication Mode. The bit is set when the slave MCU waits for an address byte to be received. When the MCU has been addressed, the MCU switches off the MPCM bit, and starts data reception.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRA>
<UCSRB>
<NAME>UCSRB</NAME>
<DESCRIPTION>UART Control an Status register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE</NAME>
<DESCRIPTION>UART Data Register Empty Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CHR9</NAME>
<DESCRIPTION>9-bit Characters</DESCRIPTION>
<TEXT>When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB8</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>When CHR9 is set (one), RXB8 is the 9th data bit of the received character.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB8</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSRB>
<UBRRHI>
<NAME>UBRRHI</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRRHI3</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRRHI2</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRRHI1</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRRHI0</NAME>
<DESCRIPTION>UART Baud Rate Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRRHI>
<UBRR>
<NAME>UBRR</NAME>
<DESCRIPTION>UART Baud Rate Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>UART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>UART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>UART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>UART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>UART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>UART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>UART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>UART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR>
</UART>
<TWI>
<LIST>[TWBR:TWCR:TWSR:TWDR:TWAR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID>TWI_01</ID>
<TEXT>TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protoco</TEXT>
<TWBR>
<NAME>TWBR</NAME>
<DESCRIPTION>TWI Bit Rate register</DESCRIPTION>
<TEXT>TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWBR7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWBR6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWBR5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWBR4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWBR3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWBR2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWBR1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWBR0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWBR>
<TWCR>
<NAME>TWCR</NAME>
<DESCRIPTION>TWI Control Register</DESCRIPTION>
<TEXT>The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.</TEXT>
<IO_ADDR>$36</IO_ADDR>
<MEM_ADDR>$56</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWINT</NAME>
<DESCRIPTION>TWI Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWEA</NAME>
<DESCRIPTION>TWI Enable Acknowledge Bit</DESCRIPTION>
<TEXT>The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWSTA</NAME>
<DESCRIPTION>TWI Start Condition Bit</DESCRIPTION>
<TEXT>The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWSTO</NAME>
<DESCRIPTION>TWI Stop Condition Bit</DESCRIPTION>
<TEXT>Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWWC</NAME>
<DESCRIPTION>TWI Write Collition Flag</DESCRIPTION>
<TEXT>The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWEN</NAME>
<DESCRIPTION>TWI Enable Bit</DESCRIPTION>
<TEXT>The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT0>
<NAME>TWIE</NAME>
<DESCRIPTION>TWI Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWCR>
<TWSR>
<NAME>TWSR</NAME>
<DESCRIPTION>TWI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWS7</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWS6</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWS5</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWS4</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWS3</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</TWSR>
<TWDR>
<NAME>TWDR</NAME>
<DESCRIPTION>TWI Data register</DESCRIPTION>
<TEXT>In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl</TEXT>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWD7</NAME>
<DESCRIPTION>TWI Data Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWD6</NAME>
<DESCRIPTION>TWI Data Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWD5</NAME>
<DESCRIPTION>TWI Data Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWD4</NAME>
<DESCRIPTION>TWI Data Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWD3</NAME>
<DESCRIPTION>TWI Data Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWD2</NAME>
<DESCRIPTION>TWI Data Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWD1</NAME>
<DESCRIPTION>TWI Data Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWD0</NAME>
<DESCRIPTION>TWI Data Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</TWDR>
<TWAR>
<NAME>TWAR</NAME>
<DESCRIPTION>TWI (Slave) Address register</DESCRIPTION>
<TEXT>The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera</TEXT>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWA6</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWA5</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWA4</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWA3</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWA2</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWA1</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWA0</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWGCE</NAME>
<DESCRIPTION>TWI General Call Recognition Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWAR>
</TWI>
<PORTA>
<LIST>[PORTA:DDRA:PINA]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTA>
<NAME>PORTA</NAME>
<DESCRIPTION>Port A Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTA7</NAME>
<DESCRIPTION>Port A Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTA6</NAME>
<DESCRIPTION>Port A Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTA5</NAME>
<DESCRIPTION>Port A Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTA4</NAME>
<DESCRIPTION>Port A Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTA3</NAME>
<DESCRIPTION>Port A Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTA2</NAME>
<DESCRIPTION>Port A Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTA1</NAME>
<DESCRIPTION>Port A Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTA0</NAME>
<DESCRIPTION>Port A Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTA>
<DDRA>
<NAME>DDRA</NAME>
<DESCRIPTION>Port A Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDA7</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDA6</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDA5</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDA4</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDA3</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDA2</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDA1</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDA0</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRA>
<PINA>
<NAME>PINA</NAME>
<DESCRIPTION>Port A Input Pins</DESCRIPTION>
<TEXT>The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINA7</NAME>
<DESCRIPTION>Input Pins, Port A bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINA6</NAME>
<DESCRIPTION>Input Pins, Port A bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINA5</NAME>
<DESCRIPTION>Input Pins, Port A bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINA4</NAME>
<DESCRIPTION>Input Pins, Port A bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINA3</NAME>
<DESCRIPTION>Input Pins, Port A bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINA2</NAME>
<DESCRIPTION>Input Pins, Port A bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINA1</NAME>
<DESCRIPTION>Input Pins, Port A bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINA0</NAME>
<DESCRIPTION>Input Pins, Port A bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT0>
</PINA>
</PORTA>
<PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Port B Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTB7</NAME>
<DESCRIPTION>Port B Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTB6</NAME>
<DESCRIPTION>Port B Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION>Port B Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION>Port B Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION>Port B Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION>Port B Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION>Port B Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION>Port B Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Port B Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDB7</NAME>
<DESCRIPTION>Port B Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDB6</NAME>
<DESCRIPTION>Port B Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION>Port B Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION>Port B Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION>Port B Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION>Port B Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION>Port B Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION>Port B Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Port B Input Pins</DESCRIPTION>
<TEXT>The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINB7</NAME>
<DESCRIPTION>Port B Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINB6</NAME>
<DESCRIPTION>Port B Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION>Port B Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION>Port B Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION>Port B Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION>Port B Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION>Port B Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION>Port B Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTC>
<LIST>[PORTC:DDRC:PINC]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTC>
<NAME>PORTC</NAME>
<DESCRIPTION>Port C Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTC7</NAME>
<DESCRIPTION>Port C Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTC6</NAME>
<DESCRIPTION>Port C Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTC5</NAME>
<DESCRIPTION>Port C Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTC4</NAME>
<DESCRIPTION>Port C Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTC3</NAME>
<DESCRIPTION>Port C Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTC2</NAME>
<DESCRIPTION>Port C Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTC1</NAME>
<DESCRIPTION>Port C Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTC0</NAME>
<DESCRIPTION>Port C Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTC>
<DDRC>
<NAME>DDRC</NAME>
<DESCRIPTION>Port C Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDC7</NAME>
<DESCRIPTION>Port C Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDC6</NAME>
<DESCRIPTION>Port C Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDC5</NAME>
<DESCRIPTION>Port C Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDC4</NAME>
<DESCRIPTION>Port C Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDC3</NAME>
<DESCRIPTION>Port C Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDC2</NAME>
<DESCRIPTION>Port C Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDC1</NAME>
<DESCRIPTION>Port C Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDC0</NAME>
<DESCRIPTION>Port C Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRC>
<PINC>
<NAME>PINC</NAME>
<DESCRIPTION>Port C Input Pins</DESCRIPTION>
<TEXT>The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINC7</NAME>
<DESCRIPTION>Port C Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINC6</NAME>
<DESCRIPTION>Port C Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINC5</NAME>
<DESCRIPTION>Port C Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINC4</NAME>
<DESCRIPTION>Port C Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINC3</NAME>
<DESCRIPTION>Port C Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINC2</NAME>
<DESCRIPTION>Port C Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINC1</NAME>
<DESCRIPTION>Port C Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINC0</NAME>
<DESCRIPTION>Port C Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINC>
</PORTC>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Port D Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTD7</NAME>
<DESCRIPTION>Port D Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTD6</NAME>
<DESCRIPTION>Port D Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTD5</NAME>
<DESCRIPTION>Port D Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTD4</NAME>
<DESCRIPTION>Port D Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTD3</NAME>
<DESCRIPTION>Port D Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTD2</NAME>
<DESCRIPTION>Port D Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION>Port D Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION>Port D Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DESCRIPTION>Port D Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDD7</NAME>
<DESCRIPTION>Port D Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDD6</NAME>
<DESCRIPTION>Port D Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDD5</NAME>
<DESCRIPTION>Port D Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDD4</NAME>
<DESCRIPTION>Port D Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDD3</NAME>
<DESCRIPTION>Port D Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDD2</NAME>
<DESCRIPTION>Port D Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION>Port D Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION>Port D Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Port D Input Pins</DESCRIPTION>
<TEXT>The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PIND7</NAME>
<DESCRIPTION>Port D Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PIND6</NAME>
<DESCRIPTION>Port D Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PIND5</NAME>
<DESCRIPTION>Port D Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PIND4</NAME>
<DESCRIPTION>Port D Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PIND3</NAME>
<DESCRIPTION>Port D Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PIND2</NAME>
<DESCRIPTION>Port D Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION>Port D Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION>Port D Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<ANALOG_COMPARATOR>
<LIST>[SFIOR:ACSR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_01</ID>
<TEXT/>
<SFIOR>
<NAME>SFIOR</NAME>
<DESCRIPTION>Special Function IO Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>ACME</NAME>
<DESCRIPTION>Analog Comparator Multiplexer Enable</DESCRIPTION>
<TEXT>When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
</SFIOR>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACD</NAME>
<DESCRIPTION>Analog Comparator Disable</DESCRIPTION>
<TEXT>When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ACBG</NAME>
<DESCRIPTION>Analog Comparator Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ACO</NAME>
<DESCRIPTION>Analog Compare Output</DESCRIPTION>
<TEXT>The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ACI</NAME>
<DESCRIPTION>Analog Comparator Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ACIE</NAME>
<DESCRIPTION>Analog Comparator Interrupt Enable</DESCRIPTION>
<TEXT>When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ACIC</NAME>
<DESCRIPTION>Analog Comparator Input Capture Enable</DESCRIPTION>
<TEXT>When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ACIS1</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 1</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACIS0</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 0</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
</ANALOG_COMPARATOR>
<AD_CONVERTER>
<LIST>[ADMUX:ADCSR:ADCH:ADCL]</LIST>
<LINK/>
<RULES>((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise</TEXT>
<ADMUX>
<NAME>ADMUX</NAME>
<DESCRIPTION>The ADC multiplexer Selection Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>REFS1</NAME>
<DESCRIPTION>Reference Selection Bit 1</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>REFS0</NAME>
<DESCRIPTION>Reference Selection Bit 0</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADLAR</NAME>
<DESCRIPTION>Left Adjust Result</DESCRIPTION>
<TEXT>The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MUX4</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>MUX3</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADMUX>
<ADCSR>
<NAME>ADCSR</NAME>
<ALIAS>ADCSRA</ALIAS>
<DESCRIPTION>The ADC Control and Status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADEN</NAME>
<DESCRIPTION>ADC Enable</DESCRIPTION>
<TEXT>Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADSC</NAME>
<DESCRIPTION>ADC Start Conversion</DESCRIPTION>
<TEXT>In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADFR</NAME>
<DESCRIPTION>ADC Free Running Select</DESCRIPTION>
<TEXT>When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADIF</NAME>
<DESCRIPTION>ADC Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADIE</NAME>
<DESCRIPTION>ADC Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADPS2</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADPS1</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADPS0</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSR>
<ADCH>
<NAME>ADCH</NAME>
<DESCRIPTION>ADC Data Register High Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju</TEXT>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCH7</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCH6</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCH5</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCH4</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCH3</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCH2</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCH1</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCH0</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCH>
<ADCL>
<NAME>ADCL</NAME>
<DESCRIPTION>ADC Data Register Low Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad</TEXT>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCL7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCL6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCL5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCL4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCL3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCL2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCL1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCL0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCL>
</AD_CONVERTER>
<EXTERNAL_INTERRUPT>
<LIST>[GIMSK:GIFR]</LIST>
<LINK/>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT/>
<GIMSK>
<NAME>GIMSK</NAME>
<DESCRIPTION>General Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT>When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</GIMSK>
<GIFR>
<NAME>GIFR</NAME>
<DESCRIPTION>General Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3A</IO_ADDR>
<MEM_ADDR>$5A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT>When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT>When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</GIFR>
</EXTERNAL_INTERRUPT>
<BOOT_LOAD>
<LIST>[SPMCR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>The Boot Loader Support provides a mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.</TEXT>
<SPMCR>
<NAME>SPMCR</NAME>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>ASB</NAME>
<DESCRIPTION>Application section busy</DESCRIPTION>
<TEXT>Application section busy</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>ASRE</NAME>
<DESCRIPTION>Application section read enable</DESCRIPTION>
<TEXT>Application section read enable</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BLBSET</NAME>
<DESCRIPTION>Boot Lock Bit Set</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for det</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no e</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCR>
</BOOT_LOAD>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[SIMULATOR:STK500:STK500_2]</MODULE_LIST><SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<EEINTERRUPT>0x1e</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<NmbIOModules>11</NmbIOModules>
<PORTA>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTA>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTB>
<PORTC>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTC>
<PORTD>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTD>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x02</IntVector>
<EnableIOAdr>0x3B</EnableIOAdr>
<EnableMask>0x40</EnableMask>
<FlagIOAdr>0x3A</FlagIOAdr>
<FlagMask>0x40</FlagMask>
<ExtPinIOAdr>0x10</ExtPinIOAdr>
<ExtPinMask>0x04</ExtPinMask>
<SenseIOAdr>0x35</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<EXTINT1>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x04</IntVector>
<EnableIOAdr>0x3B</EnableIOAdr>
<EnableMask>0x80</EnableMask>
<FlagIOAdr>0x3A</FlagIOAdr>
<FlagMask>0x80</FlagMask>
<ExtPinIOAdr>0x10</ExtPinIOAdr>
<ExtPinMask>0x08</ExtPinMask>
<SenseIOAdr>0x35</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT1>
<TIMER0>
<ID>AVRSimIOTimert81.SimIOTimert81</ID>
<IntVector>0x12</IntVector>
<ExtPinIOAdr>0x16</ExtPinIOAdr>
<ExtPinMask>0x01</ExtPinMask>
</TIMER0>
<TIMER1>
<ID>AVRSimIOTimert16pwm1.SimIOTimert16pwm1</ID>
<IcpVector>0x0A</IcpVector>
<CompAVector>0x0C</CompAVector>
<CompBVector>0x0E</CompBVector>
<OvfVector>0x10</OvfVector>
<CountPinAdr>0x16</CountPinAdr>
<CountPinMask>0x02</CountPinMask>
<IcpPinAdr>0x10</IcpPinAdr>
<IcpPinMask>0x40</IcpPinMask>
<OutputAAdr>0x10</OutputAAdr>
<OutputAMask>0x20</OutputAMask>
<OutputBAdr>0x10</OutputBAdr>
<OutputBMask>0x10</OutputBMask>
</TIMER1>
<TIMER2>
<ID>AVRSimIOTimert8pwm1.SimIOTimert8pwm1</ID>
<CompVector>0x06</CompVector>
<OvfVector>0x08</OvfVector>
<OutputAdr>0x18</OutputAdr>
<OutputMask>0x80</OutputMask>
<CountAdr>0x10</CountAdr>
<CountMask>0x80</CountMask>
</TIMER2>
<SPI>
<ID>AVRSimIOSpi.SimIOSpi</ID>
<IntVector>0x14</IntVector>
<SCKAddress>0x16</SCKAddress>
<SCKMask>0x80</SCKMask>
<MISOAddress>0x16</MISOAddress>
<MISOMask>0x40</MISOMask>
<MOSIAddress>0x16</MOSIAddress>
<MOSIMask>0x20</MOSIMask>
<SSAddress>0x16</SSAddress>
<DIRAddress>0x17</DIRAddress>
<SSMask>0x10</SSMask>
</SPI>
<UART>
<ID>AVRSimIOUart.SimIOUart</ID>
<RXVector>0x16</RXVector>
<TXVector>0x1A</TXVector>
<UDREVector>0x18</UDREVector>
<TXPinAddress>0x10</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0x10</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</UART>
<ANALOGCOMP>
<ID>AVRSimAC.SimIOAC</ID>
<IntVector>0x20</IntVector>
</ANALOGCOMP>
<DEFAULT_SETTINGS>
<HighFuse>0x99</HighFuse>
<ExtendedFuse>0xff</ExtendedFuse>
<LowFuse>0xe1</LowFuse>
<Lockbit>0xff</Lockbit>
</DEFAULT_SETTINGS>
</SIMULATOR>
<STK500>
<DeviceId>0x81</DeviceId>
<SelfTimed>1</SelfTimed>
<FullParallel>1</FullParallel>
<Polled>1</Polled>
<FPoll>0xFF</FPoll>
<EPol1>0xFF</EPol1>
<EPol2>0xFF</EPol2>
<ComLockFuseRead>0</ComLockFuseRead>
</STK500>
<STK500_2><IspEnterProgMode><timeout>200</timeout><stabDelay>100</stabDelay><cmdexeDelay>25</cmdexeDelay><synchLoops>32</synchLoops><byteDelay>0</byteDelay><pollIndex>3</pollIndex><pollValue>0x53</pollValue></IspEnterProgMode><IspLeaveProgMode><preDelay>1</preDelay><postDelay>1</postDelay></IspLeaveProgMode><IspChipErase><eraseDelay>33</eraseDelay><pollMethod>0</pollMethod></IspChipErase><IspProgramFlash><mode>0x11</mode><blockSize>64</blockSize><delay>20</delay><cmd1>0x40</cmd1><cmd2>0x4C</cmd2><cmd3>0x20</cmd3><pollVal1>0xFF</pollVal1><pollVal2>0x00</pollVal2></IspProgramFlash><IspProgramEeprom><mode>0x04</mode><blockSize>128</blockSize><delay>5</delay><cmd1>0xC0</cmd1><cmd2>0x00</cmd2><cmd3>0xA0</cmd3><pollVal1>0xFF</pollVal1><pollVal2>0xFF</pollVal2></IspProgramEeprom><IspReadFlash><blockSize>256</blockSize></IspReadFlash><IspReadEeprom><blockSize>256</blockSize></IspReadEeprom><IspReadFuse><pollIndex>4</pollIndex></IspReadFuse><IspReadLock><pollIndex>4</pollIndex></IspReadLock><IspReadSign><pollIndex>4</pollIndex></IspReadSign><IspReadOsccal><pollIndex>4</pollIndex></IspReadOsccal><PPControlStack>0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00</PPControlStack><PpEnterProgMode><stabDelay>100</stabDelay><progModeDelay>0</progModeDelay><latchCycles>0</latchCycles><toggleVtg>0</toggleVtg><powerOffDelay>0</powerOffDelay><resetDelayMs>0</resetDelayMs><resetDelayUs>0</resetDelayUs></PpEnterProgMode><PpLeaveProgMode><stabDelay>15</stabDelay><resetDelay>15</resetDelay></PpLeaveProgMode><PpChipErase><pulseWidth>0</pulseWidth><pollTimeout>30</pollTimeout></PpChipErase><PpProgramFlash><pollTimeout>15</pollTimeout><mode>0x0F</mode><blockSize>256</blockSize></PpProgramFlash><PpReadFlash><blockSize>256</blockSize></PpReadFlash><PpProgramEeprom><pollTimeout>5</pollTimeout><mode>0x00</mode><blockSize>256</blockSize></PpProgramEeprom><PpReadEeprom><blockSize>256</blockSize></PpReadEeprom><PpProgramFuse><pulseWidth>0</pulseWidth><pollTimeout>2</pollTimeout></PpProgramFuse><PpProgramLock><pulseWidth>0</pulseWidth><pollTimeout>2</pollTimeout></PpProgramLock></STK500_2></ICE_SETTINGS></AVRPART>
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