<AVRPART><MODULE_LIST>[ADMIN:FUSE:INTERRUPT_VECTOR:MEMORY:POWER:PACKAGE:CORE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS]</MODULE_LIST><ADMIN>
<PART_NAME>ATmega406</PART_NAME>
<SPEED>1MHZ</SPEED>
<BUILD>180</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$95</ADDR001>
<ADDR002>$07</ADDR002>
</SIGNATURE>
</ADMIN>
<FUSE>
<LIST>[LOW:HIGH]</LIST>
<ID/>
<ICON/>
<TEXT/>
<LOW>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>WDTON</NAME>
<TEXT>Watchdog Timer Always On</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>EESAVE</NAME>
<TEXT>EEPROM memory is preserved through the chip erase</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>BOOTSZ1</NAME>
<TEXT>Select boot size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>BOOTSZ0</NAME>
<TEXT>Select boot size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>BOOTRST</NAME>
<TEXT>Select reset vector</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>SUT1</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>SUT0</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>CKSEL</NAME>
<TEXT>Clock Selection</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>13</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Watchdog timer always on; [WDTON=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Flash section size=256 words Boot start address=$4F00; [BOOTSZ=11]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Flash section size=512 words Boot start address=$4E00; [BOOTSZ=10]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Flash section size=1024 words Boot start address=$4C00; [BOOTSZ=01]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Flash section size=2048 words Boot start address=$4800; [BOOTSZ=00] ; default value</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x07</MASK>
<VALUE>0x00</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=0 SUT=00]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x07</MASK>
<VALUE>0x02</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=0 SUT=01]</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x07</MASK>
<VALUE>0x04</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=0 SUT=10]</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x07</MASK>
<VALUE>0x01</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=1 SUT=00]</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x07</MASK>
<VALUE>0x03</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=1 SUT=01]</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x07</MASK>
<VALUE>0x05</VALUE>
<TEXT>CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=1 SUT=10]</TEXT>
</TEXT13>
</LOW>
<HIGH>
<NMB_FUSE_BITS>2</NMB_FUSE_BITS>
<FUSE1>
<NAME>OCDEN</NAME>
<TEXT>Enable OCD</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>JTAGEN</NAME>
<TEXT>Enable JTAG</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE0>
<NMB_TEXT>2</NMB_TEXT>
<TEXT1>
<MASK>0x02</MASK>
<VALUE>0x00</VALUE>
<TEXT>On-Chip Debug Enabled; [OCDEN=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>JTAG Interface Enabled; [JTAGEN=0]</TEXT>
</TEXT2>
</HIGH>
</FUSE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>23</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset</DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>BPINT</SOURCE>
<DEFINITION>Battery Protection Interrupt</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt Request 0</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt Request 1</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>INT2</SOURCE>
<DEFINITION>External Interrupt Request 2</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>INT3</SOURCE>
<DEFINITION>External Interrupt Request 3</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>PCINT0</SOURCE>
<DEFINITION>Pin Change Interrupt 0</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$00E</PROGRAM_ADDRESS>
<SOURCE>PCINT1</SOURCE>
<DEFINITION>Pin Change Interrupt 1</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$010</PROGRAM_ADDRESS>
<SOURCE>WDT</SOURCE>
<DEFINITION>Watchdog Timeout Interrupt</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$0012</PROGRAM_ADDRESS>
<SOURCE>WAKE_UP</SOURCE>
<DEFINITION>Wakeup timer overflow</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$014</PROGRAM_ADDRESS>
<SOURCE>TIM1_COMP</SOURCE>
<DEFINITION>Timer/Counter 1 Compare Match</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$016</PROGRAM_ADDRESS>
<SOURCE>TIM1_OVF</SOURCE>
<DEFINITION>Timer/Counter 1 Overflow</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$018</PROGRAM_ADDRESS>
<SOURCE>TIM0_COMPA</SOURCE>
<DEFINITION>Timer/Counter0 Compare A Match</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$01A</PROGRAM_ADDRESS>
<SOURCE>TIM0_COMPB</SOURCE>
<DEFINITION>Timer/Counter0 Compare B Match</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$001C</PROGRAM_ADDRESS>
<SOURCE>TIM0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR15>
<VECTOR16>
<PROGRAM_ADDRESS>$001E</PROGRAM_ADDRESS>
<SOURCE>TWI_BUS_CD</SOURCE>
<DEFINITION>Two-Wire Bus Connect/Disconnect</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR16>
<VECTOR17>
<PROGRAM_ADDRESS>$0020</PROGRAM_ADDRESS>
<SOURCE>TWI</SOURCE>
<DEFINITION>Two-Wire Serial Interface</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR17>
<VECTOR18>
<PROGRAM_ADDRESS>$0022</PROGRAM_ADDRESS>
<SOURCE>VADC</SOURCE>
<DEFINITION>Voltage ADC Conversion Complete</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR18>
<VECTOR19>
<PROGRAM_ADDRESS>$0024</PROGRAM_ADDRESS>
<SOURCE>CCADC_CONV</SOURCE>
<DEFINITION>Coulomb Counter ADC Conversion Complete</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR19>
<VECTOR20>
<PROGRAM_ADDRESS>$0026</PROGRAM_ADDRESS>
<SOURCE>CCADC_REG_CUR</SOURCE>
<DEFINITION>Coloumb Counter ADC Regular Current</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR20>
<VECTOR21>
<PROGRAM_ADDRESS>$0028</PROGRAM_ADDRESS>
<SOURCE>CCADC_ACC</SOURCE>
<DEFINITION>Coloumb Counter ADC Accumulator</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR21>
<VECTOR22>
<PROGRAM_ADDRESS>$02A</PROGRAM_ADDRESS>
<SOURCE>EE READY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR22>
<VECTOR23>
<PROGRAM_ADDRESS>$02C</PROGRAM_ADDRESS>
<SOURCE>SPM READY</SOURCE>
<DEFINITION>Store Program Memory Ready</DEFINITION>
<ENABLEADDRESS/>
<ENABLEMASK/>
<FLAGADDRESS/>
<FLAGMASK/>
<FLAGVALUE/>
</VECTOR23>
</INTERRUPT_VECTOR>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>40960</PROG_FLASH>
<EEPROM>512</EEPROM>
<INT_SRAM>
<SIZE>2048</SIZE>
<START_ADDR>$100</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>0</SIZE>
<START_ADDR>N/A</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>$60</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>$FF</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$FF</MEM_STOP_ADDR>
<BPPLR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF8</MEM_ADDR>
<BPPL_MASK>0x01</BPPL_MASK><BPPLE_MASK>0x02</BPPLE_MASK></BPPLR>
<BPCR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF7</MEM_ADDR>
<CCD_MASK>0x01</CCD_MASK><DCD_MASK>0x02</DCD_MASK><SCD_MASK>0x04</SCD_MASK><DUVD_MASK>0x08</DUVD_MASK></BPCR>
<CBPTR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF6</MEM_ADDR>
<OCPT0_MASK>0x01</OCPT0_MASK><OCPT1_MASK>0x02</OCPT1_MASK><OCPT2_MASK>0x04</OCPT2_MASK><OCPT3_MASK>0x08</OCPT3_MASK><SCPT0_MASK>0x10</SCPT0_MASK><SCPT1_MASK>0x20</SCPT1_MASK><SCPT2_MASK>0x40</SCPT2_MASK><SCPT3_MASK>0x80</SCPT3_MASK></CBPTR>
<BPOCD>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF5</MEM_ADDR>
<CCDL0_MASK>0x01</CCDL0_MASK><CCDL1_MASK>0x02</CCDL1_MASK><CCDL2_MASK>0x04</CCDL2_MASK><CCDL3_MASK>0x08</CCDL3_MASK><DCDL0_MASK>0x10</DCDL0_MASK><DCDL1_MASK>0x20</DCDL1_MASK><DCDL2_MASK>0x40</DCDL2_MASK><DCDL3_MASK>0x80</DCDL3_MASK></BPOCD>
<BPSCD>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF4</MEM_ADDR>
<SCDL0_MASK>0x01</SCDL0_MASK><SCDL1_MASK>0x02</SCDL1_MASK><SCDL2_MASK>0x04</SCDL2_MASK><SCDL3_MASK>0x08</SCDL3_MASK></BPSCD>
<BPDUV>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF3</MEM_ADDR>
<DUDL0_MASK>0x01</DUDL0_MASK><DUDL1_MASK>0x02</DUDL1_MASK><DUDL2_MASK>0x04</DUDL2_MASK><DUDL3_MASK>0x08</DUDL3_MASK><DUVT0_MASK>0x10</DUVT0_MASK><DUVT1_MASK>0x20</DUVT1_MASK></BPDUV>
<BPIR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF2</MEM_ADDR>
<SCIE_MASK>0x01</SCIE_MASK><DOCIE_MASK>0x02</DOCIE_MASK><COCIE_MASK>0x04</COCIE_MASK><DUVIE_MASK>0x08</DUVIE_MASK><SCIF_MASK>0x10</SCIF_MASK><DOCIF_MASK>0x20</DOCIF_MASK><COCIF_MASK>0x40</COCIF_MASK><DUVIF_MASK>0x80</DUVIF_MASK></BPIR>
<CBCR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF1</MEM_ADDR>
<CBE1_MASK>0x01</CBE1_MASK><CBE2_MASK>0x02</CBE2_MASK><CBE3_MASK>0x04</CBE3_MASK><CBE4_MASK>0x08</CBE4_MASK></CBCR>
<FCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF0</MEM_ADDR>
<PFD_MASK>0x01</PFD_MASK><CFE_MASK>0x02</CFE_MASK><DFE_MASK>0x04</DFE_MASK><CPS_MASK>0x08</CPS_MASK><PWMOPC_MASK>0x10</PWMOPC_MASK><PWMOC_MASK>0x20</PWMOC_MASK></FCSR>
<CADICH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE9</MEM_ADDR>
<CADICH0_MASK>0x01</CADICH0_MASK><CADICH1_MASK>0x02</CADICH1_MASK><CADICH2_MASK>0x04</CADICH2_MASK><CADICH3_MASK>0x08</CADICH3_MASK><CADICH4_MASK>0x10</CADICH4_MASK><CADICH5_MASK>0x20</CADICH5_MASK><CADICH6_MASK>0x40</CADICH6_MASK><CADICH7_MASK>0x80</CADICH7_MASK></CADICH>
<CADICL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE8</MEM_ADDR>
<CADICL0_MASK>0x01</CADICL0_MASK><CADICL1_MASK>0x02</CADICL1_MASK><CADICL2_MASK>0x04</CADICL2_MASK><CADICL3_MASK>0x08</CADICL3_MASK><CADICL4_MASK>0x10</CADICL4_MASK><CADICL5_MASK>0x20</CADICL5_MASK><CADICL6_MASK>0x40</CADICL6_MASK><CADICL7_MASK>0x80</CADICL7_MASK></CADICL>
<CADRDC>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE7</MEM_ADDR>
<CADRDC0_MASK>0x01</CADRDC0_MASK><CADRDC1_MASK>0x02</CADRDC1_MASK><CADRDC2_MASK>0x04</CADRDC2_MASK><CADRDC3_MASK>0x08</CADRDC3_MASK><CADRDC4_MASK>0x10</CADRDC4_MASK><CADRDC5_MASK>0x20</CADRDC5_MASK><CADRDC6_MASK>0x40</CADRDC6_MASK><CADRDC7_MASK>0x80</CADRDC7_MASK></CADRDC>
<CADRCC>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE6</MEM_ADDR>
<CADRCC0_MASK>0x01</CADRCC0_MASK><CADRCC1_MASK>0x02</CADRCC1_MASK><CADRCC2_MASK>0x04</CADRCC2_MASK><CADRCC3_MASK>0x08</CADRCC3_MASK><CADRCC4_MASK>0x10</CADRCC4_MASK><CADRCC5_MASK>0x20</CADRCC5_MASK><CADRCC6_MASK>0x40</CADRCC6_MASK><CADRCC7_MASK>0x80</CADRCC7_MASK></CADRCC>
<CADCSRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE5</MEM_ADDR>
<CADICIF_MASK>0x01</CADICIF_MASK><CADRCIF_MASK>0x02</CADRCIF_MASK><CADACIF_MASK>0x04</CADACIF_MASK><CADICIE_MASK>0x10</CADICIE_MASK><CADRCIE_MASK>0x20</CADRCIE_MASK><CADACIE_MASK>0x40</CADACIE_MASK></CADCSRB>
<CADCSRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE4</MEM_ADDR>
<CADSE_MASK>0x01</CADSE_MASK><CADSI0_MASK>0x02</CADSI0_MASK><CADSI1_MASK>0x04</CADSI1_MASK><CADAS0_MASK>0x08</CADAS0_MASK><CADAS1_MASK>0x10</CADAS1_MASK><CADUB_MASK>0x20</CADUB_MASK><CADEN_MASK>0x80</CADEN_MASK></CADCSRA>
<CADAC3>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE3</MEM_ADDR>
<CADAC24_MASK>0x01</CADAC24_MASK><CADAC25_MASK>0x02</CADAC25_MASK><CADAC26_MASK>0x04</CADAC26_MASK><CADAC27_MASK>0x08</CADAC27_MASK><CADAC28_MASK>0x10</CADAC28_MASK><CADAC29_MASK>0x20</CADAC29_MASK><CADAC30_MASK>0x40</CADAC30_MASK><CADAC31_MASK>0x80</CADAC31_MASK></CADAC3>
<CADAC2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE2</MEM_ADDR>
<CADAC16_MASK>0x01</CADAC16_MASK><CADAC17_MASK>0x02</CADAC17_MASK><CADAC18_MASK>0x04</CADAC18_MASK><CADAC19_MASK>0x08</CADAC19_MASK><CADAC20_MASK>0x10</CADAC20_MASK><CADAC21_MASK>0x20</CADAC21_MASK><CADAC22_MASK>0x40</CADAC22_MASK><CADAC23_MASK>0x80</CADAC23_MASK></CADAC2>
<CADAC1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE1</MEM_ADDR>
<CADAC08_MASK>0x01</CADAC08_MASK><CADAC09_MASK>0x02</CADAC09_MASK><CADAC10_MASK>0x04</CADAC10_MASK><CADAC11_MASK>0x08</CADAC11_MASK><CADAC12_MASK>0x10</CADAC12_MASK><CADAC13_MASK>0x20</CADAC13_MASK><CADAC14_MASK>0x40</CADAC14_MASK><CADAC15_MASK>0x80</CADAC15_MASK></CADAC1>
<CADAC0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE0</MEM_ADDR>
<CADAC00_MASK>0x01</CADAC00_MASK><CADAC01_MASK>0x02</CADAC01_MASK><CADAC02_MASK>0x04</CADAC02_MASK><CADAC03_MASK>0x08</CADAC03_MASK><CADAC04_MASK>0x10</CADAC04_MASK><CADAC05_MASK>0x20</CADAC05_MASK><CADAC06_MASK>0x40</CADAC06_MASK><CADAC07_MASK>0x80</CADAC07_MASK></CADAC0>
<BGCRR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD1</MEM_ADDR>
<BGCR0_MASK>0x01</BGCR0_MASK><BGCR1_MASK>0x02</BGCR1_MASK><BGCR2_MASK>0x04</BGCR2_MASK><BGCR3_MASK>0x08</BGCR3_MASK><BGCR4_MASK>0x10</BGCR4_MASK><BGCR5_MASK>0x20</BGCR5_MASK><BGCR6_MASK>0x40</BGCR6_MASK><BGCR7_MASK>0x80</BGCR7_MASK></BGCRR>
<BGCCR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD0</MEM_ADDR>
<BGCC0_MASK>0x01</BGCC0_MASK><BGCC1_MASK>0x02</BGCC1_MASK><BGCC2_MASK>0x04</BGCC2_MASK><BGCC3_MASK>0x08</BGCC3_MASK><BGCC4_MASK>0x10</BGCC4_MASK><BGCC5_MASK>0x20</BGCC5_MASK><BGD_MASK>0x80</BGD_MASK></BGCCR>
<CCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC0</MEM_ADDR>
<ACS_MASK>0x01</ACS_MASK><XOE_MASK>0x02</XOE_MASK></CCSR>
<TWBCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBE</MEM_ADDR>
<TWBCIP_MASK>0x01</TWBCIP_MASK><TWBDT0_MASK>0x02</TWBDT0_MASK><TWBDT1_MASK>0x04</TWBDT1_MASK><TWBCIE_MASK>0x40</TWBCIE_MASK><TWBCIF_MASK>0x80</TWBCIF_MASK></TWBCSR>
<TWAMR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBD</MEM_ADDR>
<TWAM0_MASK>0x02</TWAM0_MASK><TWAM1_MASK>0x04</TWAM1_MASK><TWAM2_MASK>0x08</TWAM2_MASK><TWAM3_MASK>0x10</TWAM3_MASK><TWAM4_MASK>0x20</TWAM4_MASK><TWAM5_MASK>0x40</TWAM5_MASK><TWAM6_MASK>0x80</TWAM6_MASK></TWAMR>
<TWCR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBC</MEM_ADDR>
<TWIE_MASK>0x01</TWIE_MASK><TWEN_MASK>0x04</TWEN_MASK><TWWC_MASK>0x08</TWWC_MASK><TWSTO_MASK>0x10</TWSTO_MASK><TWSTA_MASK>0x20</TWSTA_MASK><TWEA_MASK>0x40</TWEA_MASK><TWINT_MASK>0x80</TWINT_MASK></TWCR>
<TWDR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBB</MEM_ADDR>
<TWD0_MASK>0x01</TWD0_MASK><TWD1_MASK>0x02</TWD1_MASK><TWD2_MASK>0x04</TWD2_MASK><TWD3_MASK>0x08</TWD3_MASK><TWD4_MASK>0x10</TWD4_MASK><TWD5_MASK>0x20</TWD5_MASK><TWD6_MASK>0x40</TWD6_MASK><TWD7_MASK>0x80</TWD7_MASK></TWDR>
<TWAR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBA</MEM_ADDR>
<TWGCE_MASK>0x01</TWGCE_MASK><TWA0_MASK>0x02</TWA0_MASK><TWA1_MASK>0x04</TWA1_MASK><TWA2_MASK>0x08</TWA2_MASK><TWA3_MASK>0x10</TWA3_MASK><TWA4_MASK>0x20</TWA4_MASK><TWA5_MASK>0x40</TWA5_MASK><TWA6_MASK>0x80</TWA6_MASK></TWAR>
<TWSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xB9</MEM_ADDR>
<TWPS0_MASK>0x01</TWPS0_MASK><TWPS1_MASK>0x02</TWPS1_MASK><TWS3_MASK>0x08</TWS3_MASK><TWS4_MASK>0x10</TWS4_MASK><TWS5_MASK>0x20</TWS5_MASK><TWS6_MASK>0x40</TWS6_MASK><TWS7_MASK>0x80</TWS7_MASK></TWSR>
<TWBR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xB8</MEM_ADDR>
<TWBR0_MASK>0x01</TWBR0_MASK><TWBR1_MASK>0x02</TWBR1_MASK><TWBR2_MASK>0x04</TWBR2_MASK><TWBR3_MASK>0x08</TWBR3_MASK><TWBR4_MASK>0x10</TWBR4_MASK><TWBR5_MASK>0x20</TWBR5_MASK><TWBR6_MASK>0x40</TWBR6_MASK><TWBR7_MASK>0x80</TWBR7_MASK></TWBR>
<OCR1AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x89</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1AH>
<OCR1AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x88</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1AL>
<TCNT1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x85</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x84</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<TCCR1B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x81</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><CTC1_MASK>0x08</CTC1_MASK></TCCR1B>
<DIDR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7E</MEM_ADDR>
<VADC0D_MASK>0x01</VADC0D_MASK><VADC1D_MASK>0x02</VADC1D_MASK><VADC2D_MASK>0x04</VADC2D_MASK><VADC3D_MASK>0x08</VADC3D_MASK></DIDR0>
<VADMUX>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7C</MEM_ADDR>
<VADMUX0_MASK>0x01</VADMUX0_MASK><VADMUX1_MASK>0x02</VADMUX1_MASK><VADMUX2_MASK>0x04</VADMUX2_MASK><VADMUX3_MASK>0x08</VADMUX3_MASK></VADMUX>
<VADCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7A</MEM_ADDR>
<VADCCIE_MASK>0x01</VADCCIE_MASK><VADCCIF_MASK>0x02</VADCCIF_MASK><VADSC_MASK>0x04</VADSC_MASK><VADEN_MASK>0x08</VADEN_MASK></VADCSR>
<VADCH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x79</MEM_ADDR>
<VADC8_MASK>0x01</VADC8_MASK><VADC9_MASK>0x02</VADC9_MASK><VADC10_MASK>0x04</VADC10_MASK><VADC11_MASK>0x08</VADC11_MASK></VADCH>
<VADCL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x78</MEM_ADDR>
<VADC0_MASK>0x01</VADC0_MASK><VADC1_MASK>0x02</VADC1_MASK><VADC2_MASK>0x04</VADC2_MASK><VADC3_MASK>0x08</VADC3_MASK><VADC4_MASK>0x10</VADC4_MASK><VADC5_MASK>0x20</VADC5_MASK><VADC6_MASK>0x40</VADC6_MASK><VADC7_MASK>0x80</VADC7_MASK></VADCL>
<TIMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6F</MEM_ADDR>
<TOIE1_MASK>0x01</TOIE1_MASK><OCIE1A_MASK>0x02</OCIE1A_MASK></TIMSK1>
<TIMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6E</MEM_ADDR>
<TOIE0_MASK>0x01</TOIE0_MASK><OCIE0A_MASK>0x02</OCIE0A_MASK><OCIE0B_MASK>0x04</OCIE0B_MASK></TIMSK0>
<PCMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6C</MEM_ADDR>
<PCINT8_MASK>0x01</PCINT8_MASK><PCINT9_MASK>0x02</PCINT9_MASK><PCINT10_MASK>0x04</PCINT10_MASK><PCINT11_MASK>0x08</PCINT11_MASK><PCINT12_MASK>0x10</PCINT12_MASK><PCINT13_MASK>0x20</PCINT13_MASK><PCINT14_MASK>0x40</PCINT14_MASK><PCINT15_MASK>0x80</PCINT15_MASK></PCMSK1>
<PCMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6B</MEM_ADDR>
<PCINT0_MASK>0x01</PCINT0_MASK><PCINT1_MASK>0x02</PCINT1_MASK><PCINT2_MASK>0x04</PCINT2_MASK><PCINT3_MASK>0x08</PCINT3_MASK><PCINT4_MASK>0x10</PCINT4_MASK><PCINT5_MASK>0x20</PCINT5_MASK><PCINT6_MASK>0x40</PCINT6_MASK><PCINT7_MASK>0x80</PCINT7_MASK></PCMSK0>
<EICRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x69</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><ISC20_MASK>0x10</ISC20_MASK><ISC21_MASK>0x20</ISC21_MASK><ISC30_MASK>0x40</ISC30_MASK><ISC31_MASK>0x80</ISC31_MASK></EICRA>
<PCICR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x68</MEM_ADDR>
<PCIE0_MASK>0x01</PCIE0_MASK><PCIE1_MASK>0x02</PCIE1_MASK></PCICR>
<FOSCCAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x66</MEM_ADDR>
<FCAL0_MASK>0x01</FCAL0_MASK><FCAL1_MASK>0x02</FCAL1_MASK><FCAL2_MASK>0x04</FCAL2_MASK><FCAL3_MASK>0x08</FCAL3_MASK><FCAL4_MASK>0x10</FCAL4_MASK><FCAL5_MASK>0x20</FCAL5_MASK><FCAL6_MASK>0x40</FCAL6_MASK><FCAL7_MASK>0x80</FCAL7_MASK></FOSCCAL>
<PRR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x64</MEM_ADDR>
<PRVADC_MASK>0x01</PRVADC_MASK><PRTIM0_MASK>0x02</PRTIM0_MASK><PRTIM1_MASK>0x04</PRTIM1_MASK><PRTWI_MASK>0x08</PRTWI_MASK></PRR0>
<WUTCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x62</MEM_ADDR>
<WUTP0_MASK>0x01</WUTP0_MASK><WUTP1_MASK>0x02</WUTP1_MASK><WUTP2_MASK>0x04</WUTP2_MASK><WUTE_MASK>0x08</WUTE_MASK><WUTR_MASK>0x10</WUTR_MASK><WUTCF_MASK>0x20</WUTCF_MASK><WUTIE_MASK>0x40</WUTIE_MASK><WUTIF_MASK>0x80</WUTIF_MASK></WUTCSR>
<WDTCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x60</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDCE_MASK>0x10</WDCE_MASK><WDP3_MASK>0x20</WDP3_MASK><WDIE_MASK>0x40</WDIE_MASK><WDIF_MASK>0x80</WDIF_MASK></WDTCSR>
<SREG>
<IO_ADDR>0x3F</IO_ADDR>
<MEM_ADDR>0x5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>0x3E</IO_ADDR>
<MEM_ADDR>0x5E</MEM_ADDR>
<SP8_MASK>0x01</SP8_MASK><SP9_MASK>0x02</SP9_MASK><SP10_MASK>0x04</SP10_MASK><SP11_MASK>0x08</SP11_MASK><SP12_MASK>0x10</SP12_MASK><SP13_MASK>0x20</SP13_MASK><SP14_MASK>0x40</SP14_MASK><SP15_MASK>0x80</SP15_MASK></SPH>
<SPL>
<IO_ADDR>0x3D</IO_ADDR>
<MEM_ADDR>0x5D</MEM_ADDR>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<SPMCSR>
<IO_ADDR>0x37</IO_ADDR>
<MEM_ADDR>0x57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><BLBSET_MASK>0x08</BLBSET_MASK><RWWSRE_MASK>0x10</RWWSRE_MASK><SIGRD_MASK>0x20</SIGRD_MASK><RWWSB_MASK>0x40</RWWSB_MASK><SPMIE_MASK>0x80</SPMIE_MASK></SPMCSR>
<MCUCR>
<IO_ADDR>0x35</IO_ADDR>
<MEM_ADDR>0x55</MEM_ADDR>
<IVCE_MASK>0x01</IVCE_MASK><IVSEL_MASK>0x02</IVSEL_MASK><PUD_MASK>0x10</PUD_MASK><JTD_MASK>0x80</JTD_MASK></MCUCR>
<MCUSR>
<IO_ADDR>0x34</IO_ADDR>
<MEM_ADDR>0x54</MEM_ADDR>
<PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BODRF_MASK>0x04</BODRF_MASK><WDRF_MASK>0x08</WDRF_MASK><JTRF_MASK>0x10</JTRF_MASK></MCUSR>
<SMCR>
<IO_ADDR>0x33</IO_ADDR>
<MEM_ADDR>0x53</MEM_ADDR>
<SE_MASK>0x01</SE_MASK><SM0_MASK>0x02</SM0_MASK><SM1_MASK>0x04</SM1_MASK><SM2_MASK>0x08</SM2_MASK></SMCR>
<OCDR>
<IO_ADDR>0x31</IO_ADDR>
<MEM_ADDR>0x51</MEM_ADDR>
</OCDR>
<GPIOR2>
<IO_ADDR>0x2B</IO_ADDR>
<MEM_ADDR>0x4B</MEM_ADDR>
<GPIOR20_MASK>0x01</GPIOR20_MASK><GPIOR21_MASK>0x02</GPIOR21_MASK><GPIOR22_MASK>0x04</GPIOR22_MASK><GPIOR23_MASK>0x08</GPIOR23_MASK><GPIOR24_MASK>0x10</GPIOR24_MASK><GPIOR25_MASK>0x20</GPIOR25_MASK><GPIOR26_MASK>0x40</GPIOR26_MASK><GPIOR27_MASK>0x80</GPIOR27_MASK></GPIOR2>
<GPIOR1>
<IO_ADDR>0x2A</IO_ADDR>
<MEM_ADDR>0x4A</MEM_ADDR>
<GPIOR10_MASK>0x01</GPIOR10_MASK><GPIOR11_MASK>0x02</GPIOR11_MASK><GPIOR12_MASK>0x04</GPIOR12_MASK><GPIOR13_MASK>0x08</GPIOR13_MASK><GPIOR14_MASK>0x10</GPIOR14_MASK><GPIOR15_MASK>0x20</GPIOR15_MASK><GPIOR16_MASK>0x40</GPIOR16_MASK><GPIOR17_MASK>0x80</GPIOR17_MASK></GPIOR1>
<OCR0B>
<IO_ADDR>0x28</IO_ADDR>
<MEM_ADDR>0x48</MEM_ADDR>
<OCR0B0_MASK>0x01</OCR0B0_MASK><OCR0B1_MASK>0x02</OCR0B1_MASK><OCR0B2_MASK>0x04</OCR0B2_MASK><OCR0B3_MASK>0x08</OCR0B3_MASK><OCR0B4_MASK>0x10</OCR0B4_MASK><OCR0B5_MASK>0x20</OCR0B5_MASK><OCR0B6_MASK>0x40</OCR0B6_MASK><OCR0B7_MASK>0x80</OCR0B7_MASK></OCR0B>
<OCR0A>
<IO_ADDR>0x27</IO_ADDR>
<MEM_ADDR>0x47</MEM_ADDR>
<OCR0A0_MASK>0x01</OCR0A0_MASK><OCR0A1_MASK>0x02</OCR0A1_MASK><OCR0A2_MASK>0x04</OCR0A2_MASK><OCR0A3_MASK>0x08</OCR0A3_MASK><OCR0A4_MASK>0x10</OCR0A4_MASK><OCR0A5_MASK>0x20</OCR0A5_MASK><OCR0A6_MASK>0x40</OCR0A6_MASK><OCR0A7_MASK>0x80</OCR0A7_MASK></OCR0A>
<TCNT0>
<IO_ADDR>0x26</IO_ADDR>
<MEM_ADDR>0x46</MEM_ADDR>
<TCNT00_MASK>0x01</TCNT00_MASK><TCNT01_MASK>0x02</TCNT01_MASK><TCNT02_MASK>0x04</TCNT02_MASK><TCNT03_MASK>0x08</TCNT03_MASK><TCNT04_MASK>0x10</TCNT04_MASK><TCNT05_MASK>0x20</TCNT05_MASK><TCNT06_MASK>0x40</TCNT06_MASK><TCNT07_MASK>0x80</TCNT07_MASK></TCNT0>
<TCCR0B>
<IO_ADDR>0x25</IO_ADDR>
<MEM_ADDR>0x45</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK><WGM02_MASK>0x08</WGM02_MASK><FOC0B_MASK>0x40</FOC0B_MASK><FOC0A_MASK>0x80</FOC0A_MASK></TCCR0B>
<TCCR0A>
<IO_ADDR>0x24</IO_ADDR>
<MEM_ADDR>0x44</MEM_ADDR>
<WGM00_MASK>0x01</WGM00_MASK><WGM01_MASK>0x02</WGM01_MASK><COM0B0_MASK>0x10</COM0B0_MASK><COM0B1_MASK>0x20</COM0B1_MASK><COM0A0_MASK>0x40</COM0A0_MASK><COM0A1_MASK>0x80</COM0A1_MASK></TCCR0A>
<GTCCR>
<IO_ADDR>0x23</IO_ADDR>
<MEM_ADDR>0x43</MEM_ADDR>
<PSRSYNC_MASK>0x01</PSRSYNC_MASK><TSM_MASK>0x80</TSM_MASK></GTCCR>
<EEARH>
<IO_ADDR>0x22</IO_ADDR>
<MEM_ADDR>0x42</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK></EEARH>
<EEARL>
<IO_ADDR>0x21</IO_ADDR>
<MEM_ADDR>0x41</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEARL>
<EEDR>
<IO_ADDR>0x20</IO_ADDR>
<MEM_ADDR>0x40</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>0x1F</IO_ADDR>
<MEM_ADDR>0x3F</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEPE_MASK>0x02</EEPE_MASK><EEMPE_MASK>0x04</EEMPE_MASK><EERIE_MASK>0x08</EERIE_MASK><EEPM0_MASK>0x10</EEPM0_MASK><EEPM1_MASK>0x20</EEPM1_MASK></EECR>
<GPIOR0>
<IO_ADDR>0x1E</IO_ADDR>
<MEM_ADDR>0x3E</MEM_ADDR>
<GPIOR00_MASK>0x01</GPIOR00_MASK><GPIOR01_MASK>0x02</GPIOR01_MASK><GPIOR02_MASK>0x04</GPIOR02_MASK><GPIOR03_MASK>0x08</GPIOR03_MASK><GPIOR04_MASK>0x10</GPIOR04_MASK><GPIOR05_MASK>0x20</GPIOR05_MASK><GPIOR06_MASK>0x40</GPIOR06_MASK><GPIOR07_MASK>0x80</GPIOR07_MASK></GPIOR0>
<EIMSK>
<IO_ADDR>0x1D</IO_ADDR>
<MEM_ADDR>0x3D</MEM_ADDR>
<INT0_MASK>0x01</INT0_MASK><INT1_MASK>0x02</INT1_MASK><INT2_MASK>0x04</INT2_MASK><INT3_MASK>0x08</INT3_MASK></EIMSK>
<EIFR>
<IO_ADDR>0x1C</IO_ADDR>
<MEM_ADDR>0x3C</MEM_ADDR>
<INTF0_MASK>0x01</INTF0_MASK><INTF1_MASK>0x02</INTF1_MASK><INTF2_MASK>0x04</INTF2_MASK><INTF3_MASK>0x08</INTF3_MASK></EIFR>
<PCIFR>
<IO_ADDR>0x1B</IO_ADDR>
<MEM_ADDR>0x3B</MEM_ADDR>
<PCIF0_MASK>0x01</PCIF0_MASK><PCIF1_MASK>0x02</PCIF1_MASK></PCIFR>
<TIFR1>
<IO_ADDR>0x16</IO_ADDR>
<MEM_ADDR>0x36</MEM_ADDR>
<TOV1_MASK>0x01</TOV1_MASK><OCF1A_MASK>0x02</OCF1A_MASK></TIFR1>
<TIFR0>
<IO_ADDR>0x15</IO_ADDR>
<MEM_ADDR>0x35</MEM_ADDR>
<TOV0_MASK>0x01</TOV0_MASK><OCF0A_MASK>0x02</OCF0A_MASK><OCF0B_MASK>0x04</OCF0B_MASK></TIFR0>
<PORTD>
<IO_ADDR>0x0B</IO_ADDR>
<MEM_ADDR>0x2B</MEM_ADDR>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK></PORTD>
<DDRD>
<IO_ADDR>0x0A</IO_ADDR>
<MEM_ADDR>0x2A</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK></DDRD>
<PIND>
<IO_ADDR>0x09</IO_ADDR>
<MEM_ADDR>0x29</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK></PIND>
<PORTC>
<IO_ADDR>0x08</IO_ADDR>
<MEM_ADDR>0x28</MEM_ADDR>
<PORTC0_MASK>0x01</PORTC0_MASK></PORTC>
<PORTB>
<IO_ADDR>0x05</IO_ADDR>
<MEM_ADDR>0x25</MEM_ADDR>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK><PORTB6_MASK>0x40</PORTB6_MASK><PORTB7_MASK>0x80</PORTB7_MASK></PORTB>
<DDRB>
<IO_ADDR>0x04</IO_ADDR>
<MEM_ADDR>0x24</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK><DDB6_MASK>0x40</DDB6_MASK><DDB7_MASK>0x80</DDB7_MASK></DDRB>
<PINB>
<IO_ADDR>0x03</IO_ADDR>
<MEM_ADDR>0x23</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK><PINB6_MASK>0x40</PINB6_MASK><PINB7_MASK>0x80</PINB7_MASK></PINB>
<PORTA>
<IO_ADDR>0x02</IO_ADDR>
<MEM_ADDR>0x22</MEM_ADDR>
<PORTA0_MASK>0x01</PORTA0_MASK><PORTA1_MASK>0x02</PORTA1_MASK><PORTA2_MASK>0x04</PORTA2_MASK><PORTA3_MASK>0x08</PORTA3_MASK><PORTA4_MASK>0x10</PORTA4_MASK><PORTA5_MASK>0x20</PORTA5_MASK><PORTA6_MASK>0x40</PORTA6_MASK><PORTA7_MASK>0x80</PORTA7_MASK></PORTA>
<DDRA>
<IO_ADDR>0x01</IO_ADDR>
<MEM_ADDR>0x21</MEM_ADDR>
<DDA0_MASK>0x01</DDA0_MASK><DDA1_MASK>0x02</DDA1_MASK><DDA2_MASK>0x04</DDA2_MASK><DDA3_MASK>0x08</DDA3_MASK><DDA4_MASK>0x10</DDA4_MASK><DDA5_MASK>0x20</DDA5_MASK><DDA6_MASK>0x40</DDA6_MASK><DDA7_MASK>0x80</DDA7_MASK></DDRA>
<PINA>
<IO_ADDR>0x00</IO_ADDR>
<MEM_ADDR>0x20</MEM_ADDR>
<PINA0_MASK>0x01</PINA0_MASK><PINA1_MASK>0x02</PINA1_MASK><PINA2_MASK>0x04</PINA2_MASK><PINA3_MASK>0x08</PINA3_MASK><PINA4_MASK>0x10</PINA4_MASK><PINA5_MASK>0x20</PINA5_MASK><PINA6_MASK>0x40</PINA6_MASK><PINA7_MASK>0x80</PINA7_MASK></PINA>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>$4800</NRWW_START_ADDR>
<NRWW_STOP_ADDR>$4FFF</NRWW_STOP_ADDR>
<RWW_START_ADDR>$0</RWW_START_ADDR>
<RWW_STOP_ADDR>$47FF</RWW_STOP_ADDR>
<PAGESIZE>64</PAGESIZE>
<BOOTSZMODE1>
<BOOTSIZE>256</BOOTSIZE>
<PAGES>4</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$4F00</BOOTSTART>
<BOOTRESET>$4F00</BOOTRESET>
</BOOTSZMODE1>
<BOOTSZMODE2>
<BOOTSIZE>512</BOOTSIZE>
<PAGES>8</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$4E00</BOOTSTART>
<BOOTRESET>$4E00</BOOTRESET>
</BOOTSZMODE2>
<BOOTSZMODE3>
<BOOTSIZE>1024</BOOTSIZE>
<PAGES>16</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$4C00</BOOTSTART>
<BOOTRESET>$4C00</BOOTRESET>
</BOOTSZMODE3>
<BOOTSZMODE4>
<BOOTSIZE>2048</BOOTSIZE>
<PAGES>32</PAGES>
<APPSTART>0</APPSTART>
<BOOTSTART>$4800</BOOTSTART>
<BOOTRESET>$4800</BOOTRESET>
</BOOTSZMODE4>
</BOOT_CONFIG>
</MEMORY>
<POWER>
<CLOCK>1MHz</CLOCK>
<TEMP>85C</TEMP>
<ACTIVE>TBD mA</ACTIVE>
<IDLE>TBD mA</IDLE>
<POWER_DOWN>TBD uA</POWER_DOWN>
</POWER>
<PACKAGE>
<PACKAGES>[LQFP]</PACKAGES>
<LQFP>
<NMB_PIN>48</NMB_PIN>
<PIN1>
<NAME>[SGND]</NAME>
<TEXT/>
</PIN1>
<PIN2>
<NAME>[PA0:ADC0:PCINT0]</NAME>
<TEXT/>
</PIN2>
<PIN3>
<NAME>[PA1:ADC1:PCINT1]</NAME>
<TEXT/>
</PIN3>
<PIN4>
<NAME>[PA2:ADC2:PCINT2]</NAME>
<TEXT/>
</PIN4>
<PIN5>
<NAME>[PA3:ADC3:PCINT3]</NAME>
<TEXT/>
</PIN5>
<PIN6>
<NAME>[VREG]</NAME>
<TEXT/>
</PIN6>
<PIN7>
<NAME>[VCC]</NAME>
<TEXT/>
</PIN7>
<PIN8>
<NAME>[GND]</NAME>
<TEXT/>
</PIN8>
<PIN9>
<NAME>[PA4:ADC4:INT0:PCINT4]</NAME>
<TEXT/>
</PIN9>
<PIN10>
<NAME>[PA5:INT1:PCINT5]</NAME>
<TEXT/>
</PIN10>
<PIN11>
<NAME>[PA6:INT2:PCINT6]</NAME>
<TEXT/>
</PIN11>
<PIN12>
<NAME>[PA7:INT3:PCINT7]</NAME>
<TEXT/>
</PIN12>
<PIN13>
<NAME>['RESET]</NAME>
<TEXT/>
</PIN13>
<PIN14>
<NAME>[XTAL1]</NAME>
<TEXT/>
</PIN14>
<PIN15>
<NAME>[XTAL2]</NAME>
<TEXT/>
</PIN15>
<PIN16>
<NAME>[GND]</NAME>
<TEXT/>
</PIN16>
<PIN17>
<NAME>[PB0:TDO:PCINT8]</NAME>
<TEXT/>
</PIN17>
<PIN18>
<NAME>[PB1:TDI:PCINT9]</NAME>
<TEXT/>
</PIN18>
<PIN19>
<NAME>[PB2:TMS:PCINT10]</NAME>
<TEXT/>
</PIN19>
<PIN20>
<NAME>[PB3:TCK:PCINT11]</NAME>
<TEXT/>
</PIN20>
<PIN21>
<NAME>[PB4:PCINT12]</NAME>
<TEXT/>
</PIN21>
<PIN22>
<NAME>[PB5:PCINT13]</NAME>
<TEXT/>
</PIN22>
<PIN23>
<NAME>[SCL]</NAME>
<TEXT/>
</PIN23>
<PIN24>
<NAME>[SDA]</NAME>
<TEXT/>
</PIN24>
<PIN25>
<NAME>[PB6:OC0A:PCINT14]</NAME>
<TEXT/>
</PIN25>
<PIN26>
<NAME>[PB7:OC0B:PCINT15]</NAME>
<TEXT/>
</PIN26>
<PIN27>
<NAME>[PD0:T0]</NAME>
<TEXT/>
</PIN27>
<PIN28>
<NAME>[PD1]</NAME>
<TEXT/>
</PIN28>
<PIN29>
<NAME>[GND]</NAME>
<TEXT/>
</PIN29>
<PIN30>
<NAME>[PC0]</NAME>
<TEXT/>
</PIN30>
<PIN31>
<NAME>[BATT]</NAME>
<TEXT/>
</PIN31>
<PIN32>
<NAME>[OPC]</NAME>
<TEXT/>
</PIN32>
<PIN33>
<NAME>[OC]</NAME>
<TEXT/>
</PIN33>
<PIN34>
<NAME>[VFET]</NAME>
<TEXT/>
</PIN34>
<PIN35>
<NAME>[OD]</NAME>
<TEXT/>
</PIN35>
<PIN36>
<NAME>[PVT]</NAME>
<TEXT/>
</PIN36>
<PIN37>
<NAME>[GND]</NAME>
<TEXT/>
</PIN37>
<PIN38>
<NAME>[PV4]</NAME>
<TEXT/>
</PIN38>
<PIN39>
<NAME>[PV3]</NAME>
<TEXT/>
</PIN39>
<PIN40>
<NAME>[PV2]</NAME>
<TEXT/>
</PIN40>
<PIN41>
<NAME>[PV1]</NAME>
<TEXT/>
</PIN41>
<PIN42>
<NAME>[NV]</NAME>
<TEXT/>
</PIN42>
<PIN43>
<NAME>[VREF]</NAME>
<TEXT/>
</PIN43>
<PIN44>
<NAME>[VREFGND]</NAME>
<TEXT/>
</PIN44>
<PIN45>
<NAME>[PPI]</NAME>
<TEXT/>
</PIN45>
<PIN46>
<NAME>[PI]</NAME>
<TEXT/>
</PIN46>
<PIN47>
<NAME>[NI]</NAME>
<TEXT/>
</PIN47>
<PIN48>
<NAME>[NNI]</NAME>
<TEXT/>
</PIN48>
</LQFP>
</PACKAGE>
<CORE>
<CORE_VERSION>V2E</CORE_VERSION>
<ID>AVRSimCoreV2.SimCoreV2</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_LOCK_BITS>6</NMB_LOCK_BITS>
<NMB_TEXT>11</NMB_TEXT>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0C</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Application Protection Mode 1: No lock on SPM and LPM in Application Section</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0C</MASK>
<VALUE>0x08</VALUE>
<TEXT>Application Protection Mode 2: SPM prohibited in Application Section</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0C</MASK>
<VALUE>0x00</VALUE>
<TEXT>Application Protection Mode 3: LPM and SPM prohibited in Application Section</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0C</MASK>
<VALUE>0x04</VALUE>
<TEXT>Application Protection Mode 4: LPM prohibited in Application Section</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section</TEXT>
</TEXT11>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT1>
<LOCKBIT2>
<NAME>BLB01</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT2>
<LOCKBIT3>
<NAME>BLB02</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT3>
<LOCKBIT4>
<NAME>BLB11</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT4>
<LOCKBIT5>
<NAME>BLB12</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT5>
</LOCKBIT>
<PROGRAMMING>
<HVInterface>
</HVInterface>
<JTAGInterface>
</JTAGInterface>
<OscCal>
<OCEntry>0x00,4.0 MHz</OCEntry>
</OscCal>
<FlashPageSize>128</FlashPageSize>
<EepromPageSize>4</EepromPageSize>
</PROGRAMMING>
<IO_MODULE><MODULE_LIST>[AD_CONVERTER:EXTERNAL_INTERRUPT:TIMER_COUNTER_1:WAKEUP_TIMER:BATTERY_PROTECTION:FET:COULOMB_COUNTER:CELL_BALANCING:CPU:WATCHDOG:TIMER_COUNTER_0:PORTA:PORTB:PORTC:PORTD:BOOT_LOAD:TWI:BANDGAP:EEPROM]</MODULE_LIST><AD_CONVERTER>
<LIST>[VADMUX:VADCH:VADCL:VADCSR]</LIST>
<LINK>[VADCH:VADCL]</LINK>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time.</TEXT>
<VADMUX>
<NAME>VADMUX</NAME>
<DESCRIPTION>The VADC multiplexer Selection Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7C</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>VADMUX3</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>VADMUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>VADMUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>VADMUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</VADMUX>
<VADCH>
<NAME>VADCH</NAME>
<DESCRIPTION>VADC Data Register High Byte</DESCRIPTION>
<TEXT>When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x79</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>VADC11</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>VADC10</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>VADC9</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>VADC8</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</VADCH>
<VADCL>
<NAME>VADCL</NAME>
<DESCRIPTION>VADC Data Register Low Byte</DESCRIPTION>
<TEXT>When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x78</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>VADC7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>VADC6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>VADC5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>VADC4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>VADC3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>VADC2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>VADC1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>VADC0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</VADCL>
<VADCSR>
<NAME>VADCSR</NAME>
<DESCRIPTION>The VADC Control and Status register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>VADEN</NAME>
<DESCRIPTION>VADC Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversion</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>VADSC</NAME>
<DESCRIPTION>VADC Satrt Conversion</DESCRIPTION>
<TEXT>Write this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>VADCCIF</NAME>
<DESCRIPTION>VADC Conversion Complete Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>VADCCIE</NAME>
<DESCRIPTION>VADC Conversion Complete Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</VADCSR>
</AD_CONVERTER>
<EXTERNAL_INTERRUPT>
<LIST>[EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0]</LIST>
<LINK>[PCMSK1:PCMSK0]</LINK>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT>The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interru</TEXT>
<EICRA>
<NAME>EICRA</NAME>
<DESCRIPTION>External Interrupt Control Register </DESCRIPTION>
<TEXT>The External Interrupt Control Register A contains control bits for interrupt sense control.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x69</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ISC31</NAME>
<DESCRIPTION>External Interrupt Sense Control 3 Bit 1 </DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ISC30</NAME>
<DESCRIPTION>External Interrupt Sense Control 3 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ISC21</NAME>
<DESCRIPTION>External Interrupt Sense Control 2 Bit 1</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ISC20</NAME>
<DESCRIPTION>External Interrupt Sense Control 2 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>External Interrupt Sense Control 1 Bit 1 </DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>External Interrupt Sense Control 1 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>External Interrupt Sense Control 0 Bit 1 </DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>External Interrupt Sense Control 0 Bit 0</DESCRIPTION>
<TEXT>The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EICRA>
<EIMSK>
<NAME>EIMSK</NAME>
<DESCRIPTION>External Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x1D</IO_ADDR>
<MEM_ADDR>0x3D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>INT3</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>INT2</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT>When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT>When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIMSK>
<EIFR>
<NAME>EIFR</NAME>
<DESCRIPTION>External Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x1C</IO_ADDR>
<MEM_ADDR>0x3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>INTF3</NAME>
<DESCRIPTION>External Interrupt Flag 3</DESCRIPTION>
<TEXT>When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>INTF2</NAME>
<DESCRIPTION>External Interrupt Flag 2</DESCRIPTION>
<TEXT>When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT>When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT>When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIFR>
<PCICR>
<NAME>PCICR</NAME>
<DESCRIPTION>Pin Change Interrupt Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x68</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>PCIE1</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 1</DESCRIPTION>
<TEXT>When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCIE0</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 0</DESCRIPTION>
<TEXT>When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCICR>
<PCIFR>
<NAME>PCIFR</NAME>
<DESCRIPTION>Pin Change Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x1B</IO_ADDR>
<MEM_ADDR>0x3B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>PCIF1</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 1</DESCRIPTION>
<TEXT>When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCIF0</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 1</DESCRIPTION>
<TEXT>When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCIFR>
<PCMSK1>
<NAME>PCMSK1</NAME>
<DESCRIPTION>Pin Change Enable Mask Register 1</DESCRIPTION>
<TEXT>Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT15</NAME>
<DESCRIPTION>Pin Change Enable Mask 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT14</NAME>
<DESCRIPTION>Pin Change Enable Mask 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT13</NAME>
<DESCRIPTION>Pin Change Enable Mask 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT12</NAME>
<DESCRIPTION>Pin Change Enable Mask 12</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT11</NAME>
<DESCRIPTION>Pin Change Enable Mask 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT10</NAME>
<DESCRIPTION>Pin Change Enable Mask 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT9</NAME>
<DESCRIPTION>Pin Change Enable Mask 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT8</NAME>
<DESCRIPTION>Pin Change Enable Mask 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK1>
<PCMSK0>
<NAME>PCMSK0</NAME>
<DESCRIPTION>Pin Change Enable Mask Register 0</DESCRIPTION>
<TEXT>Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT7</NAME>
<DESCRIPTION>Pin Change Enable Mask 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT6</NAME>
<DESCRIPTION>Pin Change Enable Mask 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT5</NAME>
<DESCRIPTION>Pin Change Enable Mask 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT4</NAME>
<DESCRIPTION>Pin Change Enable Mask 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT3</NAME>
<DESCRIPTION>Pin Change Enable Mask 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT2</NAME>
<DESCRIPTION>Pin Change Enable Mask 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT1</NAME>
<DESCRIPTION>Pin Change Enable Mask 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT0</NAME>
<DESCRIPTION>Pin Change Enable Mask 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK0>
</EXTERNAL_INTERRUPT>
<TIMER_COUNTER_1>
<LIST>[TCCR1B:TCNT1H:TCNT1L:OCR1AL:OCR1AH:TIMSK1:TIFR1:GTCCR]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1AH:OCR1AL]</LINK>
<ICON>io_timer.bmp</ICON>
<ID/>
<TEXT/>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x81</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>CTC1</NAME>
<DESCRIPTION>Clear Timer/Counter on Compare Match</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Clock Select1 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Clock Select1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Clock Select1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer Counter 1 High Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x85</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer Counter 1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x84</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer Counter 1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1AL>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Output Compare Register 1A Low byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x88</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AL>
<OCR1AH>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Output Compare Register 1A High byte</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x89</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AH>
<TIMSK1>
<NAME>TIMSK1</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>OCIE1A</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK1>
<TIFR1>
<NAME>TIFR1</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x16</IO_ADDR>
<MEM_ADDR>0x36</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>OCF1A</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Flag A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR1>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x23</IO_ADDR>
<MEM_ADDR>0x43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT0>
<NAME>PSRSYNC</NAME>
<DESCRIPTION>Prescaler Reset</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GTCCR>
</TIMER_COUNTER_1>
<WAKEUP_TIMER>
<LIST>[WUTCSR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>t8pwm1_01</ID>
<TEXT/>
<WUTCSR>
<NAME>WUTCSR</NAME>
<DESCRIPTION>Wake-up Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x62</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>WUTIF</NAME>
<DESCRIPTION>Wake-up Timer Interrupt Flag</DESCRIPTION>
<TEXT>The bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WUTIE</NAME>
<DESCRIPTION>Wake-up Timer Interrupt Enable</DESCRIPTION>
<TEXT>When the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set .</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>WUTCF</NAME>
<DESCRIPTION>Wake-up timer Calibration Flag</DESCRIPTION>
<TEXT>The WUTCF bit is set after every 256 Slow RC OScillator clocks (2 ms @ 131 kHz)</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>WUTR</NAME>
<DESCRIPTION>Wake-up Timer Reset</DESCRIPTION>
<TEXT>When WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WUTE</NAME>
<DESCRIPTION>Wake-up Timer Enable</DESCRIPTION>
<TEXT>When the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WUTP2</NAME>
<DESCRIPTION>Wake-up Timer Prescaler Bit 2</DESCRIPTION>
<TEXT>The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WUTP1</NAME>
<DESCRIPTION>Wake-up Timer Prescaler Bit 1</DESCRIPTION>
<TEXT>The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WUTP0</NAME>
<DESCRIPTION>Wake-up Timer Prescaler Bit 0</DESCRIPTION>
<TEXT>The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WUTCSR>
</WAKEUP_TIMER>
<BATTERY_PROTECTION>
<LIST>[BPPLR:BPCR:CBPTR:BPOCD:BPSCD:BPDUV:BPIR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT/>
<BPPLR>
<NAME>BPPLR</NAME>
<DESCRIPTION>Battery Protection Parameter Lock Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF8</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>BPPLE</NAME>
<DESCRIPTION>Battery Protection Parameter Lock Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>BPPL</NAME>
<DESCRIPTION>Battery Protection Parameter Lock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPPLR>
<BPCR>
<NAME>BPCR</NAME>
<DESCRIPTION>Battery Protection Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF7</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>DUVD</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SCD</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DCD</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CCD</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPCR>
<CBPTR>
<NAME>CBPTR</NAME>
<DESCRIPTION>Current Battery Protection Timing Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF6</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SCPT3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SCPT2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SCPT1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SCPT0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCPT3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCPT2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCPT1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCPT0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CBPTR>
<BPOCD>
<NAME>BPOCD</NAME>
<DESCRIPTION>Battery Protection OverCurrent Detection Level Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF5</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>DCDL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DCDL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DCDL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DCDL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CCDL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CCDL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CCDL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CCDL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPOCD>
<BPSCD>
<NAME>BPSCD</NAME>
<DESCRIPTION>Battery Protection Short-Circuit Detection Level Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF4</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>SCDL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SCDL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SCDL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SCDL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPSCD>
<BPDUV>
<NAME>BPDUV</NAME>
<DESCRIPTION>Battery Protection Deep Under Voltage Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF3</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>DUVT1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DUVT0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DUDL3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DUDL2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DUDL1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DUDL0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPDUV>
<BPIR>
<NAME>BPIR</NAME>
<DESCRIPTION>Battery Protection Interrupt Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF2</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>DUVIF</NAME>
<DESCRIPTION>Deep Under-voltage Early Warning Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COCIF</NAME>
<DESCRIPTION>Charge Over-current Protection Activated Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DOCIF</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SCIF</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DUVIE</NAME>
<DESCRIPTION>Deep Under-voltage Early Warning Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>COCIE</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DOCIE</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SCIE</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BPIR>
</BATTERY_PROTECTION>
<FET>
<LIST>[FCSR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT/>
<FCSR>
<NAME>FCSR</NAME>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF0</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PWMOC</NAME>
<DESCRIPTION>Pulse Width Modulation of OC output</DESCRIPTION>
<TEXT>When the PWMOC is cleared (zero), the CFE bit and the battery protection circuitry controls the OC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PWMOPC</NAME>
<DESCRIPTION>Pulse Width Modulation Modulation of OPC output</DESCRIPTION>
<TEXT>When the PWMOPC is cleared (zero), the PFD bit and the battery protection circuitry controls the OPC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPS</NAME>
<DESCRIPTION>Current Protection Status</DESCRIPTION>
<TEXT>The CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DFE</NAME>
<DESCRIPTION>Discharge FET Enable</DESCRIPTION>
<TEXT>When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CFE</NAME>
<DESCRIPTION>Charge FET Enable</DESCRIPTION>
<TEXT>When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PFD</NAME>
<DESCRIPTION>Precharge FET disable</DESCRIPTION>
<TEXT>The PFD bit provides complete control of the Precharge FET. When the PFD bit is cleared (zero), the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be set when CURRENT_PROTECTION is set (one).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</FCSR>
</FET>
<COULOMB_COUNTER>
<LIST>[CADCSRA:CADCSRB:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0:CADRCC:CADRDC]</LIST>
<LINK>[CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0]</LINK>
<ICON>io_analo.bmp</ICON>
<ID>CoulombCounter_m406</ID>
<TEXT/>
<CADCSRA>
<NAME>CADCSRA</NAME>
<DESCRIPTION>CC-ADC Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE4</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CADEN</NAME>
<DESCRIPTION>When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT5>
<NAME>CADUB</NAME>
<DESCRIPTION>CC_ADC Update Busy</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADAS1</NAME>
<DESCRIPTION>CC_ADC Accumulate Current Select Bit 1</DESCRIPTION>
<TEXT>The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADAS0</NAME>
<DESCRIPTION>CC_ADC Accumulate Current Select Bit 0</DESCRIPTION>
<TEXT>The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADSI1</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADSI0</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADSE</NAME>
<DESCRIPTION>When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADCSRA>
<CADCSRB>
<NAME>CADCSRB</NAME>
<DESCRIPTION>CC-ADC Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE5</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>CADACIE</NAME>
<DESCRIPTION/>
<TEXT>CC-ADC Accumulate Current Interrupt Enable </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADRCIE</NAME>
<DESCRIPTION>Regular Current Interrupt Enable</DESCRIPTION>
<TEXT>When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADICIE</NAME>
<DESCRIPTION>CAD Instantenous Current Interrupt Enable</DESCRIPTION>
<TEXT>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT2>
<NAME>CADACIF</NAME>
<DESCRIPTION>CC-ADC Accumulate Current Interrupt Flag</DESCRIPTION>
<TEXT>The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADRCIF</NAME>
<DESCRIPTION>CC-ADC Accumulate Current Interrupt Flag</DESCRIPTION>
<TEXT>The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADICIF</NAME>
<DESCRIPTION>CC-ADC Instantaneous Current Interrupt Flag </DESCRIPTION>
<TEXT>The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADCSRB>
<CADICH>
<NAME>CADICH</NAME>
<DESCRIPTION>CC-ADC Instantaneous Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE9</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADICH7</NAME>
<DESCRIPTION>When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADICH6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADICH5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADICH4</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADICH3</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADICH2</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADICH1</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADICH0</NAME>
<DESCRIPTION>When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADICH>
<CADICL>
<NAME>CADICL</NAME>
<DESCRIPTION>CC-ADC Instantaneous Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE8</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADICL7</NAME>
<DESCRIPTION>When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADICL6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADICL5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADICL4</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADICL3</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADICL2</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADICL1</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADICL0</NAME>
<DESCRIPTION>When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADICL>
<CADAC3>
<NAME>CADAC3</NAME>
<DESCRIPTION>ADC Accumulate Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE3</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADAC31</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADAC30</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADAC29</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADAC28</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADAC27</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADAC26</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADAC25</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADAC24</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADAC3>
<CADAC2>
<NAME>CADAC2</NAME>
<DESCRIPTION>ADC Accumulate Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE2</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADAC23</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADAC22</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADAC21</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADAC20</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADAC19</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADAC18</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADAC17</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADAC16</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADAC2>
<CADAC1>
<NAME>CADAC1</NAME>
<DESCRIPTION>ADC Accumulate Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE1</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADAC15</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADAC14</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADAC13</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADAC12</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADAC11</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADAC10</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADAC09</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADAC08</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADAC1>
<CADAC0>
<NAME>CADAC0</NAME>
<DESCRIPTION>ADC Accumulate Current</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE0</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADAC07</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADAC06</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADAC05</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADAC04</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADAC03</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADAC02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADAC01</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADAC00</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADAC0>
<CADRCC>
<NAME>CADRCC</NAME>
<DESCRIPTION>CC-ADC Regular Charge Current</DESCRIPTION>
<TEXT>The CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE6</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADRCC7</NAME>
<DESCRIPTION>When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADRCC6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADRCC5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADRCC4</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADRCC3</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADRCC2</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADRCC1</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADRCC0</NAME>
<DESCRIPTION>When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADRCC>
<CADRDC>
<NAME>CADRDC</NAME>
<DESCRIPTION>CC-ADC Regular Discharge Current</DESCRIPTION>
<TEXT>The CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xE7</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CADRDC7</NAME>
<DESCRIPTION>When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CADRDC6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CADRDC5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CADRDC4</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CADRDC3</NAME>
<DESCRIPTION>The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CADRDC2</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CADRDC1</NAME>
<DESCRIPTION>The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. </DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CADRDC0</NAME>
<DESCRIPTION>When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CADRDC>
</COULOMB_COUNTER>
<CELL_BALANCING>
<LIST>[CBCR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT/>
<CBCR>
<NAME>CBCR</NAME>
<DESCRIPTION>Cell Balancing Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xF1</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>CBE4</NAME>
<DESCRIPTION>Cell Balancing Enable 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CBE3</NAME>
<DESCRIPTION>Cell Balancing Enable 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CBE2</NAME>
<DESCRIPTION>Cell Balancing Enable 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CBE1</NAME>
<DESCRIPTION>Battery Protection Parameter Lock</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CBCR>
</CELL_BALANCING>
<CPU>
<LIST>[SREG:SPH:SPL:MCUCR:MCUSR:FOSCCAL:SMCR:GPIOR2:GPIOR1:GPIOR0:CCSR:DIDR0:PRR0]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x3F</IO_ADDR>
<MEM_ADDR>0x5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DESCRIPTION>Sign Bit</DESCRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R</TEXT>
<IO_ADDR>0x3E</IO_ADDR>
<MEM_ADDR>0x5E</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP15</NAME>
<DESCRIPTION>Stack pointer bit 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP14</NAME>
<DESCRIPTION>Stack pointer bit 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP13</NAME>
<DESCRIPTION>Stack pointer bit 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP12</NAME>
<DECRIPTION>Stack pointer bit 12</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP11</NAME>
<DESCRIPTION>Stack pointer bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP10</NAME>
<DESCRIPTION>Stack pointer bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP9</NAME>
<DESCRIPTION>Stack pointer bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack pointer bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt </TEXT>
<IO_ADDR>0x3D</IO_ADDR>
<MEM_ADDR>0x5D</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack pointer bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>0x35</IO_ADDR>
<MEM_ADDR>0x55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>JTD</NAME>
<DESCRIPTION>JTAG Disable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT4>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up disable</DESCRIPTION>
<TEXT>When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>IVSEL</NAME>
<DESCRIPTION>Interrupt Vector Select</DESCRIPTION>
<TEXT>When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>IVCE</NAME>
<DESCRIPTION>Interrupt Vector Change Enable</DESCRIPTION>
<TEXT>The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>0x34</IO_ADDR>
<MEM_ADDR>0x54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>JTRF</NAME>
<DESCRIPTION>JTAG Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Flag</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BODRF</NAME>
<DESCRIPTION> Brown-out Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on reset flag</DESCRIPTION>
<TEXT>This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
<FOSCCAL>
<NAME>FOSCCAL</NAME>
<DESCRIPTION>Fast Oscillator Calibration Value</DESCRIPTION>
<TEXT>Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table </TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x66</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>FCAL7</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit7</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FCAL6</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit6</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>FCAL5</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FCAL4</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>FCAL3</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>FCAL2</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>FCAL1</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>FCAL0</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</FOSCCAL>
<SMCR>
<NAME>SMCR</NAME>
<DESCRIPTION>Sleep Mode Control Register</DESCRIPTION>
<TEXT>The Sleep Mode Control Register contains control bits for power management.</TEXT>
<IO_ADDR>0x33</IO_ADDR>
<MEM_ADDR>0x53</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>SM2</NAME>
<DESCRIPTION>Sleep Mode Select bit 2</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SM1</NAME>
<DESCRIPTION>Sleep Mode Select bit 1</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep Mode Select bit 0</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SMCR>
<GPIOR2>
<NAME>GPIOR2</NAME>
<DESCRIPTION>General Purpose IO Register 2</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>0x2B</IO_ADDR>
<MEM_ADDR>0x4B</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR27</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR26</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR25</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR24</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR23</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR22</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR21</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR20</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR2>
<GPIOR1>
<NAME>GPIOR1</NAME>
<DESCRIPTION>General Purpose IO Register 1</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>0x2A</IO_ADDR>
<MEM_ADDR>0x4A</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR17</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR16</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR15</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR14</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR13</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR12</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR11</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR10</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR1>
<GPIOR0>
<NAME>GPIOR0</NAME>
<DESCRIPTION>General Purpose IO Register 0</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>0x1E</IO_ADDR>
<MEM_ADDR>0x3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR07</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR06</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR05</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR04</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR03</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR02</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR01</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR00</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR0>
<CCSR>
<NAME>CCSR</NAME>
<DESCRIPTION>Clock Control and Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xC0</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>XOE</NAME>
<DESCRIPTION>32 kHz Crystal Oscillator Enable</DESCRIPTION>
<TEXT>The XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. This allows the Oscillator clock to stabilize prior to use. The 32 kHz Crystal Oscillator requires approximately two seconds to stabilize, this must be timed by the user software. This bit must remain set as long as the ACS bit is set, otherwise the 32 kHz clock to CC-ADC and Wake-up timer will be stopped.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACS</NAME>
<DESCRIPTION>Asynchronous Clock Select</DESCRIPTION>
<TEXT>The ACS bit is used to selected the source of the asynchronous clock for the Coulomb Counter ADC and Wake-up Timer. The Slow RC Oscillator is selected when this bit is cleared (zero). The 32 kHz Crystal Oscillator is selected when this bit is set (one).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</CCSR>
<DIDR0>
<NAME>DIDR0</NAME>
<DESCRIPTION>Digital Input Disable Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x7E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>VADC3D</NAME>
<DESCRIPTION>When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>VADC2D</NAME>
<DESCRIPTION>When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>VADC1D</NAME>
<DESCRIPTION>When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>VADC0D</NAME>
<DESCRIPTION>When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DIDR0>
<PRR0>
<NAME>PRR0</NAME>
<DESCRIPTION>Power Reduction Register 0</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x64</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>PRTWI</NAME>
<DESCRIPTION>Power Reduction TWI</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRTIM1</NAME>
<DESCRIPTION>Power Reduction Timer/Counter1</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRTIM0</NAME>
<DESCRIPTION>Power Reduction Timer/Counter0</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRVADC</NAME>
<DESCRIPTION>Power Reduction V-ADC</DESCRIPTION>
<TEXT>Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PRR0>
</CPU>
<WATCHDOG>
<LIST>[WDTCSR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCSR>
<NAME>WDTCSR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x60</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>WDIF</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WDIE</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>WDP3</NAME>
<DESCRIPTION>Watchdog Timer Prescaler Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>WDCE</NAME>
<DESCRIPTION>Watchdog Change Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCSR>
</WATCHDOG>
<TIMER_COUNTER_0>
<LIST>[TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:TIMSK0:TIFR0]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>timer8_megaD</ID>
<TEXT>The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions</TEXT>
<TCCR0A>
<NAME>TCCR0A</NAME>
<DESCRIPTION>Timer/Counter0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x24</IO_ADDR>
<MEM_ADDR>0x44</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM0A1</NAME>
<DESCRIPTION>Force Output Compare</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM0A0</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM0B1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM0B0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM01</NAME>
<DESCRIPTION>Clock Select0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM00</NAME>
<DESCRIPTION>Clock Select0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0A>
<TCCR0B>
<NAME>TCCR0B</NAME>
<DESCRIPTION>Timer/Counter0 Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x25</IO_ADDR>
<MEM_ADDR>0x45</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC0A</NAME>
<DESCRIPTION>Force Output Compare</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC0B</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>WGM02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0B>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer Counter 0</DESCRIPTION>
<TEXT>The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.</TEXT>
<IO_ADDR>0x26</IO_ADDR>
<MEM_ADDR>0x46</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT07</NAME>
<DESCRIPTION>Timer Counter 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT06</NAME>
<DESCRIPTION>Timer Counter 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT05</NAME>
<DESCRIPTION>Timer Counter 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT04</NAME>
<DESCRIPTION>Timer Counter 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT03</NAME>
<DESCRIPTION>Timer Counter 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT02</NAME>
<DESCRIPTION>Timer Counter 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT01</NAME>
<DESCRIPTION>Timer Counter 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT00</NAME>
<DESCRIPTION>Timer Counter 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
<OCR0A>
<NAME>OCR0A</NAME>
<DESCRIPTION>Output compare Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x27</IO_ADDR>
<MEM_ADDR>0x47</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>OCR0A7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0A6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0A5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0A4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0A3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0A2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0A1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0A0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0A>
<OCR0B>
<NAME>OCR0B</NAME>
<DESCRIPTION>Output compare Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x28</IO_ADDR>
<MEM_ADDR>0x48</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>OCR0B7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0B6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0B5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0B4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0B3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0B2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0B1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0B0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0B>
<TIMSK0>
<NAME>TIMSK0</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCIE0B</NAME>
<DESCRIPTION>Output Compare Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE0A</NAME>
<DESCRIPTION>Output Compare Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE0</NAME>
<DESCRIPTION>Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK0>
<TIFR0>
<NAME>TIFR0</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x15</IO_ADDR>
<MEM_ADDR>0x35</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCF0B</NAME>
<DESCRIPTION>Output Compare Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF0A</NAME>
<DESCRIPTION>Output Compare Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV0</NAME>
<DESCRIPTION>Overflow Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR0>
</TIMER_COUNTER_0>
<PORTA>
<LIST>[PORTA:DDRA:PINA]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTA>
<NAME>PORTA</NAME>
<DESCRIPTION>Port A Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x02</IO_ADDR>
<MEM_ADDR>0x22</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTA7</NAME>
<DESCRIPTION>Port A Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTA6</NAME>
<DESCRIPTION>Port A Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTA5</NAME>
<DESCRIPTION>Port A Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTA4</NAME>
<DESCRIPTION>Port A Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTA3</NAME>
<DESCRIPTION>Port A Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTA2</NAME>
<DESCRIPTION>Port A Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTA1</NAME>
<DESCRIPTION>Port A Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTA0</NAME>
<DESCRIPTION>Port A Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTA>
<DDRA>
<NAME>DDRA</NAME>
<DESCRIPTION>Port A Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x01</IO_ADDR>
<MEM_ADDR>0x21</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDA7</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDA6</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDA5</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDA4</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDA3</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDA2</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDA1</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDA0</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRA>
<PINA>
<NAME>PINA</NAME>
<DESCRIPTION>Port A Input Pins</DESCRIPTION>
<TEXT>The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.</TEXT>
<IO_ADDR>0x00</IO_ADDR>
<MEM_ADDR>0x20</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINA7</NAME>
<DESCRIPTION>Input Pins, Port A bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINA6</NAME>
<DESCRIPTION>Input Pins, Port A bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINA5</NAME>
<DESCRIPTION>Input Pins, Port A bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINA4</NAME>
<DESCRIPTION>Input Pins, Port A bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINA3</NAME>
<DESCRIPTION>Input Pins, Port A bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINA2</NAME>
<DESCRIPTION>Input Pins, Port A bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINA1</NAME>
<DESCRIPTION>Input Pins, Port A bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINA0</NAME>
<DESCRIPTION>Input Pins, Port A bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT0>
</PINA>
</PORTA>
<PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Port B Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x05</IO_ADDR>
<MEM_ADDR>0x25</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTB7</NAME>
<DESCRIPTION>Port B Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTB6</NAME>
<DESCRIPTION>Port B Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION>Port B Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION>Port B Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION>Port B Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION>Port B Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION>Port B Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION>Port B Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Port B Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x04</IO_ADDR>
<MEM_ADDR>0x24</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDB7</NAME>
<DESCRIPTION>Port B Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDB6</NAME>
<DESCRIPTION>Port B Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION>Port B Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION>Port B Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION>Port B Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION>Port B Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION>Port B Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION>Port B Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Port B Input Pins</DESCRIPTION>
<TEXT>The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.</TEXT>
<IO_ADDR>0x03</IO_ADDR>
<MEM_ADDR>0x23</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINB7</NAME>
<DESCRIPTION>Port B Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINB6</NAME>
<DESCRIPTION>Port B Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION>Port B Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION>Port B Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION>Port B Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION>Port B Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION>Port B Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION>Port B Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTC>
<LIST>[PORTC]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTC>
<NAME>PORTC</NAME>
<DESCRIPTION>Port C Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x08</IO_ADDR>
<MEM_ADDR>0x28</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>PORTC0</NAME>
<DESCRIPTION>Port C Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTC>
</PORTC>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Data Register, Port D</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x0B</IO_ADDR>
<MEM_ADDR>0x2B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DIRECTION>Data Direction Register, Port D</DIRECTION>
<TEXT/>
<IO_ADDR>0x0A</IO_ADDR>
<MEM_ADDR>0x2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Input Pins, Port D</DESCRIPTION>
<TEXT/>
<IO_ADDR>0x09</IO_ADDR>
<MEM_ADDR>0x29</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<BOOT_LOAD>
<LIST>[SPMCSR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<TEXT>The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor</TEXT>
<SPMCSR>
<NAME>SPMCSR</NAME>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>0x37</IO_ADDR>
<MEM_ADDR>0x57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPMIE</NAME>
<DESCRIPTION>SPM Interrupt Enable</DESCRIPTION>
<TEXT>When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>RWWSB</NAME>
<DESCRIPTION>Read While Write Section Busy</DESCRIPTION>
<TEXT>When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SIGRD</NAME>
<DESCRIPTION>Signature Row Read</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RWWSRE</NAME>
<DESCRIPTION>Read While Write section read enable</DESCRIPTION>
<TEXT>When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BLBSET</NAME>
<DESCRIPTION>Boot Lock Bit Set</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCSR>
</BOOT_LOAD>
<TWI>
<LIST>[TWBCSR:TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI </TEXT>
<TWBCSR>
<NAME>TWBCSR</NAME>
<DESCRIPTION>TWI Bus Control and Status Register</DESCRIPTION>
<TEXT>The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configuration bit, an interrupt can be generated either when the TWI bus is connected or disconnected.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBE</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWBCIF</NAME>
<DESCRIPTION>TWI Bus Connect/Disconnect Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWBCIE</NAME>
<DESCRIPTION>TWI Bus Connect/Disconnect Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT2>
<NAME>TWBDT1</NAME>
<DESCRIPTION>TWI Bus Disconnect Time-out Period</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWBDT0</NAME>
<DESCRIPTION>TWI Bus Disconnect Time-out Period</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWBCIP</NAME>
<DESCRIPTION>TWI Bus Connect/Disconnect Interrupt Polarity</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWBCSR>
<TWAMR>
<NAME>TWAMR</NAME>
<DESCRIPTION>TWI (Slave) Address Mask Register</DESCRIPTION>
<TEXT>The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBD</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWAM6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWAM5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWAM4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWAM3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWAM2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWAM1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWAM0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TWAMR>
<TWBR>
<NAME>TWBR</NAME>
<DESCRIPTION>TWI Bit Rate register</DESCRIPTION>
<TEXT>TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xB8</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWBR7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWBR6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWBR5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWBR4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWBR3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWBR2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWBR1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWBR0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWBR>
<TWCR>
<NAME>TWCR</NAME>
<DESCRIPTION>TWI Control Register</DESCRIPTION>
<TEXT>The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBC</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWINT</NAME>
<DESCRIPTION>TWI Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWEA</NAME>
<DESCRIPTION>TWI Enable Acknowledge Bit</DESCRIPTION>
<TEXT>The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWSTA</NAME>
<DESCRIPTION>TWI Start Condition Bit</DESCRIPTION>
<TEXT>The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWSTO</NAME>
<DESCRIPTION>TWI Stop Condition Bit</DESCRIPTION>
<TEXT>Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWWC</NAME>
<DESCRIPTION>TWI Write Collition Flag</DESCRIPTION>
<TEXT>The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWEN</NAME>
<DESCRIPTION>TWI Enable Bit</DESCRIPTION>
<TEXT>The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT0>
<NAME>TWIE</NAME>
<DESCRIPTION>TWI Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWCR>
<TWSR>
<NAME>TWSR</NAME>
<DESCRIPTION>TWI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xB9</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWS7</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWS6</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWS5</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWS4</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWS3</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>TWPS1</NAME>
<DESCRIPTION>TWI Prescaler</DESCRIPTION>
<TEXT>Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWPS0</NAME>
<DESCRIPTION>TWI Prescaler</DESCRIPTION>
<TEXT>Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWSR>
<TWDR>
<NAME>TWDR</NAME>
<DESCRIPTION>TWI Data register</DESCRIPTION>
<TEXT>In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBB</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWD7</NAME>
<DESCRIPTION>TWI Data Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWD6</NAME>
<DESCRIPTION>TWI Data Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWD5</NAME>
<DESCRIPTION>TWI Data Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWD4</NAME>
<DESCRIPTION>TWI Data Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWD3</NAME>
<DESCRIPTION>TWI Data Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWD2</NAME>
<DESCRIPTION>TWI Data Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWD1</NAME>
<DESCRIPTION>TWI Data Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWD0</NAME>
<DESCRIPTION>TWI Data Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</TWDR>
<TWAR>
<NAME>TWAR</NAME>
<DESCRIPTION>TWI (Slave) Address register</DESCRIPTION>
<TEXT>The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xBA</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWA6</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWA5</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWA4</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWA3</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWA2</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWA1</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWA0</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWGCE</NAME>
<DESCRIPTION>TWI General Call Recognition Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWAR>
</TWI>
<BANDGAP>
<LIST>[BGCRR:BGCCR]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT/>
<BGCRR>
<NAME>BGCRR</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD1</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>BGCR7</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>BGCR6</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>BGCR5</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>BGCR4</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BGCR3</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BGCR2</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>BGCR1</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>BGCR0</NAME>
<DESCRIPTION>Bandgap Calibration of Resistor Ladder Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BGCRR>
<BGCCR>
<NAME>BGCCR</NAME>
<DESCRIPTION>Bandgap Calibration Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0xD0</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>BGD</NAME>
<DESCRIPTION>Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT5>
<NAME>BGCC5</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>BGCC4</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 4</DESCRIPTION>
<TEXT>These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BGCC3</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 3</DESCRIPTION>
<TEXT>These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BGCC2</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 2</DESCRIPTION>
<TEXT>These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>BGCC1</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 1</DESCRIPTION>
<TEXT>These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>BGCC0</NAME>
<DESCRIPTION>BG Calibration of PTAT Current Bit 0</DESCRIPTION>
<TEXT>These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</BGCCR>
</BANDGAP>
<EEPROM>
<LIST>[EEARH:EEARL:EEDR:EECR]</LIST>
<LINK>[EEARH:EEARL]</LINK>
<ICON>io_cpu.bmp</ICON>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Address Register High Byte</DESCRIPTION>
<TEXT/>
<ICON>io_cpu.bmp</ICON>
<IO_ADDR>0x22</IO_ADDR>
<MEM_ADDR>0x42</MEM_ADDR>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT/>
<ICON>io_cpu.bmp</ICON>
<IO_ADDR>0x21</IO_ADDR>
<MEM_ADDR>0x41</MEM_ADDR>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<ICON>io_cpu.bmp</ICON>
<IO_ADDR>0x20</IO_ADDR>
<MEM_ADDR>0x40</MEM_ADDR>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<ICON>io_flag.bmp</ICON>
<IO_ADDR>0x1F</IO_ADDR>
<MEM_ADDR>0x3F</MEM_ADDR>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>EEPM1</NAME>
<DESCRIPTION>EEPROM Programming Mode Bits</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEPM0</NAME>
<DESCRIPTION>EEPROM Programming Mode Bits</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMPE</NAME>
<DESCRIPTION>EEPROM Master Programming Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
<ALIAS>EEMWE</ALIAS>
</BIT2>
<BIT1>
<NAME>EEPE</NAME>
<DESCRIPTION>EEPROM Programming Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
<ALIAS>EEWE</ALIAS>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[JTAGICEmkII:STK500:SIMULATOR:STK500_2]</MODULE_LIST><JTAGICEmkII>
<ID>0x0950703F</ID>
<Interface>JTAG</Interface>
<!--Bit 0 in byte 0 is I/O location, bit 7 in byte 7 is I/O location 63-->
<ucRead>0x3F,0x0F,0x60,0xF8,0xFF,0x0D,0xB8,0xE0</ucRead>
<ucWrite>0x37,0x0F,0x00,0xE0,0xFF,0x0D,0xB8,0xE0</ucWrite>
<ucReadShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucReadShadow>
<ucWriteShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucWriteShadow>
<!--Bit 0 in byte 0 is extended I/O location 96, bit 7 in byte 19 is I/O location 255-->
<ucExtRead>0x55,0xDB,0x00,0x57,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x7F,0x01,0x00,0x03,0x00,0xFF,0x03,0xFF,0x01</ucExtRead>
<ucExtWrite>0x50,0xDB,0x00,0x50,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x6D,0x01,0x00,0x03,0x00,0xD0,0x00,0xFB,0x00</ucExtWrite>
<ucExtReadShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtReadShadow>
<ucExtWriteShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtWriteShadow>
<!--Register locations etc.-->
<ucIDRAddress>0x31</ucIDRAddress>
<ucSPMCAddress>0X57</ucSPMCAddress>
<ucRAMPZAddress>0X00</ucRAMPZAddress>
<ulFlashPageSize>128</ulFlashPageSize>
<ulEepromPageSize>4</ulEepromPageSize>
<ulBootAddress>0x4F00</ulBootAddress>
<BootAddress11>0x4F00</BootAddress11>
<BootAddress10>0x4E00</BootAddress10>
<BootAddress01>0x4C00</BootAddress01>
<BootAddress00>0x4800</BootAddress00>
<ucUpperExtIOLoc>0xF8</ucUpperExtIOLoc>
<ulFlashSize>0xA000</ulFlashSize>
<ulRegStart>0x0000,32</ulRegStart>
<ulIoStart>0x0020,64</ulIoStart>
<!--Other stuff-->
<DWENmaskExt>0x00</DWENmaskExt>
<DWENmaskHigh>0x00</DWENmaskHigh>
<DWENmaskLow>0x00</DWENmaskLow>
<SPIENmaskExt>0x00</SPIENmaskExt>
<SPIENmaskHigh>0x00</SPIENmaskHigh>
<SPIENmaskLow>0x00</SPIENmaskLow>
<ucEepromInst>0x00</ucEepromInst>
<ucFlashInst>0x00</ucFlashInst>
<ucSPHaddr>0x3e</ucSPHaddr>
<ucSPLaddr>0x3d</ucSPLaddr>
<DWdatareg>0x00</DWdatareg>
<DWbasePC>0x00</DWbasePC>
<ucAllowFullPageBitstream>0x00</ucAllowFullPageBitstream>
<uiStartSmallestBootLoaderSection>0x00</uiStartSmallestBootLoaderSection>
<ucUseJTAGID>0x01</ucUseJTAGID>
<EnablePageProgramming>0x01</EnablePageProgramming>
<CacheType>0x00</CacheType>
<EECRAddress>0x3f</EECRAddress>
<Issues>
<ID>0x0950703F</ID>
<Message>Part revision not supported by AVR Studio.</Message>
</Issues>
</JTAGICEmkII>
<STK500>
<DeviceId>0x70</DeviceId>
<SelfTimed>0</SelfTimed>
<FullParallel>1</FullParallel>
<Polled>1</Polled>
<FPoll>0xFF</FPoll>
<EPol1>0xFF</EPol1>
<EPol2>0xFF</EPol2>
<ComLockFuseRead>0</ComLockFuseRead>
<ResetDisable>0</ResetDisable>
</STK500>
<SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<NmbIOModules>13</NmbIOModules>
<EEINTERRUPT>0x2a</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<PORTA>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTA>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTB>
<PORTC>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>N</TOGGLE_PIN>
</PORTC>
<PORTD>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTD>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0004</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x01</EnableMask>
<FlagIOAdr>0x3A</FlagIOAdr>
<FlagMask>0x01</FlagMask>
<ExtPinIOAdr>0x00</ExtPinIOAdr>
<ExtPinMask>0x10</ExtPinMask>
<SenseIOAdr>0x69</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<EXTINT1>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0006</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x02</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x02</FlagMask>
<ExtPinIOAdr>0x00</ExtPinIOAdr>
<ExtPinMask>0x20</ExtPinMask>
<SenseIOAdr>0x69</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT1>
<EXTINT2>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0008</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x04</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x04</FlagMask>
<ExtPinIOAdr>0x00</ExtPinIOAdr>
<ExtPinMask>0x40</ExtPinMask>
<SenseIOAdr>0x69</SenseIOAdr>
<SenseMask>0x30</SenseMask>
</EXTINT2>
<EXTINT3>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x000A</IntVector>
<EnableIOAdr>0x1D</EnableIOAdr>
<EnableMask>0x08</EnableMask>
<FlagIOAdr>0x1C</FlagIOAdr>
<FlagMask>0x08</FlagMask>
<ExtPinIOAdr>0x00</ExtPinIOAdr>
<ExtPinMask>0x80</ExtPinMask>
<SenseIOAdr>0x69</SenseIOAdr>
<SenseMask>0xc0</SenseMask>
</EXTINT3>
<PININT0>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x0c</IntVector>
<EnableIOAdr>0x68</EnableIOAdr>
<EnableMask>0x01</EnableMask>
<FlagIOAdr>0x1b</FlagIOAdr>
<FlagMask>0x01</FlagMask>
<ExtPinIOAdr>0x00</ExtPinIOAdr>
<ExtPinMask>0xff</ExtPinMask>
<PCMaskIOAdr>0x6b</PCMaskIOAdr>
</PININT0>
<PININT1>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x0e</IntVector>
<EnableIOAdr>0x68</EnableIOAdr>
<EnableMask>0x02</EnableMask>
<FlagIOAdr>0x1b</FlagIOAdr>
<FlagMask>0x02</FlagMask>
<ExtPinIOAdr>0x03</ExtPinIOAdr>
<ExtPinMask>0xff</ExtPinMask>
<PCMaskIOAdr>0x6c</PCMaskIOAdr>
</PININT1>
<TIMER0>
<ID>AvrSimIOTim8pwmsync2.tim8pwmsync2</ID>
<OvfVector>0x001c</OvfVector>
<CompAVector>0x0018</CompAVector>
<CompBVector>0x001a</CompBVector>
<OCnAport>PORTB</OCnAport>
<OCnAbit>6</OCnAbit>
<OCnBport>PORTB</OCnBport>
<OCnBbit>7</OCnBbit>
<TxPort>PORTD</TxPort>
<TxBit>0</TxBit>
</TIMER0>
<TWI>
<ID>AvrSimTWI.SimTWI</ID>
<IntVector>0x0016</IntVector>
</TWI>
<SPM>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<IntVector>0x2c</IntVector>
</SPM>
<DEFAULT_SETTINGS>
<HighFuse>0x99</HighFuse>
<ExtendedFuse>0xff</ExtendedFuse>
<LowFuse>0xe1</LowFuse>
<Lockbit>0xff</Lockbit>
</DEFAULT_SETTINGS>
</SIMULATOR>
<STK500_2><PPControlStack>0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00</PPControlStack><PpEnterProgMode><stabDelay>100</stabDelay><progModeDelay>0</progModeDelay><latchCycles>6</latchCycles><toggleVtg>0</toggleVtg><powerOffDelay>0</powerOffDelay><resetDelayMs>0</resetDelayMs><resetDelayUs>0</resetDelayUs></PpEnterProgMode><PpLeaveProgMode><stabDelay>15</stabDelay><resetDelay>15</resetDelay></PpLeaveProgMode><PpChipErase><pulseWidth>0</pulseWidth><pollTimeout>10</pollTimeout></PpChipErase><PpProgramFlash><pollTimeout>5</pollTimeout><mode>0x0F</mode><blockSize>256</blockSize></PpProgramFlash><PpReadFlash><blockSize>256</blockSize></PpReadFlash><PpProgramEeprom><pollTimeout>5</pollTimeout><mode>0x07</mode><blockSize>256</blockSize></PpProgramEeprom><PpReadEeprom><blockSize>256</blockSize></PpReadEeprom><PpProgramFuse><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramFuse><PpProgramLock><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramLock></STK500_2></ICE_SETTINGS></AVRPART>
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