<AVRPART><MODULE_LIST>[CORE:INTERRUPT_VECTOR:LOCKBIT:POWER:PROGVOLT:PROGRAMMING:PACKAGE:ADMIN:MEMORY:FUSE:IO_MODULE:ICE_SETTINGS]</MODULE_LIST><CORE>
<CORE_VERSION>V3</CORE_VERSION>
<ID>AVRSimCore32.SimCoreV3</ID>
<NEW_INSTRUCTIONS>[]</NEW_INSTRUCTIONS>
<INSTRUCTIONS_NOT_SUPPORTED>[]</INSTRUCTIONS_NOT_SUPPORTED>
<RAMP_REGISTERS>[]</RAMP_REGISTERS>
<GP_REG_FILE>
<NMB_REG>32</NMB_REG>
<START_ADDR>$00</START_ADDR>
<X_REG_HIGH>$1B</X_REG_HIGH>
<X_REG_LOW>$1A</X_REG_LOW>
<Y_REG_HIGH>$1D</Y_REG_HIGH>
<Y_REG_LOW>$1C</Y_REG_LOW>
<Z_REG_HIGH>$1F</Z_REG_HIGH>
<Z_REG_LOW>$1E</Z_REG_LOW>
</GP_REG_FILE>
</CORE>
<INTERRUPT_VECTOR>
<NMB_VECTORS>57</NMB_VECTORS>
<VECTOR1>
<PROGRAM_ADDRESS>$000</PROGRAM_ADDRESS>
<SOURCE>RESET</SOURCE>
<DEFINITION>External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. </DEFINITION>
</VECTOR1>
<VECTOR2>
<PROGRAM_ADDRESS>$002</PROGRAM_ADDRESS>
<SOURCE>INT0</SOURCE>
<DEFINITION>External Interrupt Request 0</DEFINITION>
</VECTOR2>
<VECTOR3>
<PROGRAM_ADDRESS>$004</PROGRAM_ADDRESS>
<SOURCE>INT1</SOURCE>
<DEFINITION>External Interrupt Request 1</DEFINITION>
</VECTOR3>
<VECTOR4>
<PROGRAM_ADDRESS>$006</PROGRAM_ADDRESS>
<SOURCE>INT2</SOURCE>
<DEFINITION>External Interrupt Request 2</DEFINITION>
</VECTOR4>
<VECTOR5>
<PROGRAM_ADDRESS>$008</PROGRAM_ADDRESS>
<SOURCE>INT3</SOURCE>
<DEFINITION>External Interrupt Request 3</DEFINITION>
</VECTOR5>
<VECTOR6>
<PROGRAM_ADDRESS>$00A</PROGRAM_ADDRESS>
<SOURCE>INT4</SOURCE>
<DEFINITION>External Interrupt Request 4</DEFINITION>
</VECTOR6>
<VECTOR7>
<PROGRAM_ADDRESS>$00C</PROGRAM_ADDRESS>
<SOURCE>INT5</SOURCE>
<DEFINITION>External Interrupt Request 5</DEFINITION>
</VECTOR7>
<VECTOR8>
<PROGRAM_ADDRESS>$00E</PROGRAM_ADDRESS>
<SOURCE>INT6</SOURCE>
<DEFINITION>External Interrupt Request 6</DEFINITION>
</VECTOR8>
<VECTOR9>
<PROGRAM_ADDRESS>$010</PROGRAM_ADDRESS>
<SOURCE>INT7</SOURCE>
<DEFINITION>External Interrupt Request 7</DEFINITION>
</VECTOR9>
<VECTOR10>
<PROGRAM_ADDRESS>$012</PROGRAM_ADDRESS>
<SOURCE>PCINT0</SOURCE>
<DEFINITION>Pin Change Interrupt Request 0</DEFINITION>
</VECTOR10>
<VECTOR11>
<PROGRAM_ADDRESS>$014</PROGRAM_ADDRESS>
<SOURCE>PCINT1</SOURCE>
<DEFINITION>Pin Change Interrupt Request 1</DEFINITION>
</VECTOR11>
<VECTOR12>
<PROGRAM_ADDRESS>$016</PROGRAM_ADDRESS>
<SOURCE>PCINT2</SOURCE>
<DEFINITION>Pin Change Interrupt Request 2</DEFINITION>
</VECTOR12>
<VECTOR13>
<PROGRAM_ADDRESS>$018</PROGRAM_ADDRESS>
<SOURCE>WDT</SOURCE>
<DEFINITION>Watchdog Time-out Interrupt</DEFINITION>
</VECTOR13>
<VECTOR14>
<PROGRAM_ADDRESS>$01A</PROGRAM_ADDRESS>
<SOURCE>TIMER2_COMPA</SOURCE>
<DEFINITION>Timer/Counter2 Compare Match A</DEFINITION>
</VECTOR14>
<VECTOR15>
<PROGRAM_ADDRESS>$01C</PROGRAM_ADDRESS>
<SOURCE>TIMER2_COMPB</SOURCE>
<DEFINITION>Timer/Counter2 Compare Match B</DEFINITION>
</VECTOR15>
<VECTOR16>
<PROGRAM_ADDRESS>$01E</PROGRAM_ADDRESS>
<SOURCE>TIMER2_OVF</SOURCE>
<DEFINITION>Timer/Counter2 Overflow</DEFINITION>
</VECTOR16>
<VECTOR17>
<PROGRAM_ADDRESS>$020</PROGRAM_ADDRESS>
<SOURCE>TIMER1_CAPT</SOURCE>
<DEFINITION>Timer/Counter1 Capture Event</DEFINITION>
</VECTOR17>
<VECTOR18>
<PROGRAM_ADDRESS>$022</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPA</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match A</DEFINITION>
</VECTOR18>
<VECTOR19>
<PROGRAM_ADDRESS>$024</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPB</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match B</DEFINITION>
</VECTOR19>
<VECTOR20>
<PROGRAM_ADDRESS>$026</PROGRAM_ADDRESS>
<SOURCE>TIMER1_COMPC</SOURCE>
<DEFINITION>Timer/Counter1 Compare Match C</DEFINITION>
</VECTOR20>
<VECTOR21>
<PROGRAM_ADDRESS>$028</PROGRAM_ADDRESS>
<SOURCE>TIMER1_OVF</SOURCE>
<DEFINITION>Timer/Counter1 Overflow</DEFINITION>
</VECTOR21>
<VECTOR22>
<PROGRAM_ADDRESS>$02A</PROGRAM_ADDRESS>
<SOURCE>TIMER0_COMPA</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match A</DEFINITION>
</VECTOR22>
<VECTOR23>
<PROGRAM_ADDRESS>$02C</PROGRAM_ADDRESS>
<SOURCE>TIMER0_COMPB</SOURCE>
<DEFINITION>Timer/Counter0 Compare Match B</DEFINITION>
</VECTOR23>
<VECTOR24>
<PROGRAM_ADDRESS>$02E</PROGRAM_ADDRESS>
<SOURCE>TIMER0_OVF</SOURCE>
<DEFINITION>Timer/Counter0 Overflow</DEFINITION>
</VECTOR24>
<VECTOR25>
<PROGRAM_ADDRESS>$030</PROGRAM_ADDRESS>
<SOURCE>SPI, STC</SOURCE>
<DEFINITION>SPI Serial Transfer Complete</DEFINITION>
</VECTOR25>
<VECTOR26>
<PROGRAM_ADDRESS>$032</PROGRAM_ADDRESS>
<SOURCE>USART0, RX</SOURCE>
<DEFINITION>USART0, Rx Complete</DEFINITION>
</VECTOR26>
<VECTOR27>
<PROGRAM_ADDRESS>$034</PROGRAM_ADDRESS>
<SOURCE>USART0, UDRE</SOURCE>
<DEFINITION>USART0 Data register Empty</DEFINITION>
</VECTOR27>
<VECTOR28>
<PROGRAM_ADDRESS>$036</PROGRAM_ADDRESS>
<SOURCE>USART0, TX</SOURCE>
<DEFINITION>USART0, Tx Complete</DEFINITION>
</VECTOR28>
<VECTOR29>
<PROGRAM_ADDRESS>$038</PROGRAM_ADDRESS>
<SOURCE>ANALOG_COMP</SOURCE>
<DEFINITION>Analog Comparator</DEFINITION>
</VECTOR29>
<VECTOR30>
<PROGRAM_ADDRESS>$03A</PROGRAM_ADDRESS>
<SOURCE>ADC</SOURCE>
<DEFINITION>ADC Conversion Complete</DEFINITION>
</VECTOR30>
<VECTOR31>
<PROGRAM_ADDRESS>$03C</PROGRAM_ADDRESS>
<SOURCE>EE_READY</SOURCE>
<DEFINITION>EEPROM Ready</DEFINITION>
</VECTOR31>
<VECTOR32>
<PROGRAM_ADDRESS>$03E</PROGRAM_ADDRESS>
<SOURCE>TIMER3_CAPT</SOURCE>
<DEFINITION>Timer/Counter3 Capture Event</DEFINITION>
</VECTOR32>
<VECTOR33>
<PROGRAM_ADDRESS>$040</PROGRAM_ADDRESS>
<SOURCE>TIMER3_COMPA</SOURCE>
<DEFINITION>Timer/Counter3 Compare Match A</DEFINITION>
</VECTOR33>
<VECTOR34>
<PROGRAM_ADDRESS>$042</PROGRAM_ADDRESS>
<SOURCE>TIMER3_COMPB</SOURCE>
<DEFINITION>Timer/Counter3 Compare Match B</DEFINITION>
</VECTOR34>
<VECTOR35>
<PROGRAM_ADDRESS>$044</PROGRAM_ADDRESS>
<SOURCE>TIMER3_COMPC</SOURCE>
<DEFINITION>Timer/Counter3 Compare Match C</DEFINITION>
</VECTOR35>
<VECTOR36>
<PROGRAM_ADDRESS>$046</PROGRAM_ADDRESS>
<SOURCE>TIMER3_OVF</SOURCE>
<DEFINITION>Timer/Counter3 Overflow</DEFINITION>
</VECTOR36>
<VECTOR37>
<PROGRAM_ADDRESS>$048</PROGRAM_ADDRESS>
<SOURCE>USART1, RX</SOURCE>
<DEFINITION>USART1, Rx Complete</DEFINITION>
</VECTOR37>
<VECTOR38>
<PROGRAM_ADDRESS>$04A</PROGRAM_ADDRESS>
<SOURCE>USART1, UDRE</SOURCE>
<DEFINITION>USART1 Data register Empty</DEFINITION>
</VECTOR38>
<VECTOR39>
<PROGRAM_ADDRESS>$04C</PROGRAM_ADDRESS>
<SOURCE>USART1, TX</SOURCE>
<DEFINITION>USART1, Tx Complete</DEFINITION>
</VECTOR39>
<VECTOR40>
<PROGRAM_ADDRESS>$04E</PROGRAM_ADDRESS>
<SOURCE>TWI</SOURCE>
<DEFINITION>2-wire Serial Interface</DEFINITION>
</VECTOR40>
<VECTOR41>
<PROGRAM_ADDRESS>$050</PROGRAM_ADDRESS>
<SOURCE>SPM_READY</SOURCE>
<DEFINITION>Store Program Memory Read</DEFINITION>
</VECTOR41>
<VECTOR42>
<PROGRAM_ADDRESS>$052</PROGRAM_ADDRESS>
<SOURCE>TIMER4_CAPT</SOURCE>
<DEFINITION>Timer/Counter4 Capture Event</DEFINITION>
</VECTOR42>
<VECTOR43>
<PROGRAM_ADDRESS>$054</PROGRAM_ADDRESS>
<SOURCE>TIMER4_COMPA</SOURCE>
<DEFINITION>Timer/Counter4 Compare Match A</DEFINITION>
</VECTOR43>
<VECTOR44>
<PROGRAM_ADDRESS>$056</PROGRAM_ADDRESS>
<SOURCE>TIMER4_COMPB</SOURCE>
<DEFINITION>Timer/Counter4 Compare Match B</DEFINITION>
</VECTOR44>
<VECTOR45>
<PROGRAM_ADDRESS>$058</PROGRAM_ADDRESS>
<SOURCE>TIMER4_COMPC</SOURCE>
<DEFINITION>Timer/Counter4 Compare Match C</DEFINITION>
</VECTOR45>
<VECTOR46>
<PROGRAM_ADDRESS>$05A</PROGRAM_ADDRESS>
<SOURCE>TIMER4_OVF</SOURCE>
<DEFINITION>Timer/Counter4 Overflow</DEFINITION>
</VECTOR46>
<VECTOR47>
<PROGRAM_ADDRESS>$05C</PROGRAM_ADDRESS>
<SOURCE>TIMER5_CAPT</SOURCE>
<DEFINITION>Timer/Counter5 Capture Event</DEFINITION>
</VECTOR47>
<VECTOR48>
<PROGRAM_ADDRESS>$05E</PROGRAM_ADDRESS>
<SOURCE>TIMER5_COMPA</SOURCE>
<DEFINITION>Timer/Counter5 Compare Match A</DEFINITION>
</VECTOR48>
<VECTOR49>
<PROGRAM_ADDRESS>$060</PROGRAM_ADDRESS>
<SOURCE>TIMER5_COMPB</SOURCE>
<DEFINITION>Timer/Counter5 Compare Match B</DEFINITION>
</VECTOR49>
<VECTOR50>
<PROGRAM_ADDRESS>$062</PROGRAM_ADDRESS>
<SOURCE>TIMER5_COMPC</SOURCE>
<DEFINITION>Timer/Counter5 Compare Match C</DEFINITION>
</VECTOR50>
<VECTOR51>
<PROGRAM_ADDRESS>$064</PROGRAM_ADDRESS>
<SOURCE>TIMER5_OVF</SOURCE>
<DEFINITION>Timer/Counter5 Overflow</DEFINITION>
</VECTOR51>
<VECTOR52>
<PROGRAM_ADDRESS>$066</PROGRAM_ADDRESS>
<SOURCE>USART2, RX</SOURCE>
<DEFINITION>USART2, Rx Complete</DEFINITION>
</VECTOR52>
<VECTOR53>
<PROGRAM_ADDRESS>$068</PROGRAM_ADDRESS>
<SOURCE>USART2, UDRE</SOURCE>
<DEFINITION>USART2 Data register Empty</DEFINITION>
</VECTOR53>
<VECTOR54>
<PROGRAM_ADDRESS>$06A</PROGRAM_ADDRESS>
<SOURCE>USART2, TX</SOURCE>
<DEFINITION>USART2, Tx Complete</DEFINITION>
</VECTOR54>
<VECTOR55>
<PROGRAM_ADDRESS>$06C</PROGRAM_ADDRESS>
<SOURCE>USART3, RX</SOURCE>
<DEFINITION>USART3, Rx Complete</DEFINITION>
</VECTOR55>
<VECTOR56>
<PROGRAM_ADDRESS>$06E</PROGRAM_ADDRESS>
<SOURCE>USART3, UDRE</SOURCE>
<DEFINITION>USART3 Data register Empty</DEFINITION>
</VECTOR56>
<VECTOR57>
<PROGRAM_ADDRESS>$070</PROGRAM_ADDRESS>
<SOURCE>USART3, TX</SOURCE>
<DEFINITION>USART3, Tx Complete</DEFINITION>
</VECTOR57>
</INTERRUPT_VECTOR>
<LOCKBIT>
<ICON/>
<ID/>
<TEXT>[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled</TEXT>
<NMB_LOCK_BITS>6</NMB_LOCK_BITS>
<NMB_TEXT>11</NMB_TEXT>
<TEXT1>
<MASK>0x03</MASK>
<VALUE>0x03</VALUE>
<TEXT>Mode 1: No memory lock features enabled</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x03</MASK>
<VALUE>0x02</VALUE>
<TEXT>Mode 2: Further programming disabled</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x03</MASK>
<VALUE>0x00</VALUE>
<TEXT>Mode 3: Further programming and verification disabled</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x0C</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Application Protection Mode 1: No lock on SPM and LPM in Application Section</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x0C</MASK>
<VALUE>0x08</VALUE>
<TEXT>Application Protection Mode 2: SPM prohibited in Application Section</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x0C</MASK>
<VALUE>0x00</VALUE>
<TEXT>Application Protection Mode 3: LPM and SPM prohibited in Application Section</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x0C</MASK>
<VALUE>0x04</VALUE>
<TEXT>Application Protection Mode 4: LPM prohibited in Application Section</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x30</MASK>
<VALUE>0x30</VALUE>
<TEXT>Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x30</MASK>
<VALUE>0x20</VALUE>
<TEXT>Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x30</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x30</MASK>
<VALUE>0x10</VALUE>
<TEXT>Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section</TEXT>
</TEXT11>
<LOCKBIT0>
<NAME>LB1</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT0>
<LOCKBIT1>
<NAME>LB2</NAME>
<TEXT>Lock bit</TEXT>
</LOCKBIT1>
<LOCKBIT2>
<NAME>BLB01</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT2>
<LOCKBIT3>
<NAME>BLB02</NAME>
<TEXT>Boot Lock bit</TEXT>
</LOCKBIT3>
<LOCKBIT4>
<NAME>BLB11</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT4>
<LOCKBIT5>
<NAME>BLB12</NAME>
<TEXT>Boot lock bit</TEXT>
</LOCKBIT5>
</LOCKBIT>
<POWER>
<CLOCK>4MHz</CLOCK>
<TEMP>25C</TEMP>
<ACTIVE>5.0mA</ACTIVE>
<IDLE>2.2mA</IDLE>
<POWER_DOWN><3uA</POWER_DOWN>
</POWER>
<PROGVOLT>
<SER_PROG_MIN_V>2.7</SER_PROG_MIN_V>
<SER_PROG_MAX_V>6.0</SER_PROG_MAX_V>
<PAR_PROG_MIN_V>4.5</PAR_PROG_MIN_V>
<PAR_PROG_MAX_V>5.5</PAR_PROG_MAX_V>
</PROGVOLT>
<PROGRAMMING>
<ISPInterface>
<FuseReadMask>0xff,0xdf</FuseReadMask>
<FuseProgMask>0xff,0xdf</FuseProgMask>
<FuseWarning>1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!</FuseWarning>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
</ISPInterface>
<HVInterface>
<FuseWarning>1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!</FuseWarning>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
</HVInterface>
<JTAGInterface>
<FuseWarning>1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!</FuseWarning>
<FuseWarning>1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!</FuseWarning>
</JTAGInterface>
<OscCal>
<OCEntry>0x00,8.0 MHz</OCEntry>
</OscCal>
<FlashPageSize>256</FlashPageSize>
<EepromPageSize>8</EepromPageSize>
</PROGRAMMING>
<PACKAGE>
<PACKAGES>[TQFP]</PACKAGES>
<TQFP>
<NMB_PIN>100</NMB_PIN>
<PIN1>
<PIN_NAME>[OC0B]</PIN_NAME>
<ALT_NAME>[PG5]</ALT_NAME>
<DESCRIPTION/>
</PIN1>
<PIN2>
<PIN_NAME>[RXD:PCINT8]</PIN_NAME>
<ALT_NAME>[PE0]</ALT_NAME>
<DESCRIPTION/>
</PIN2>
<PIN3>
<PIN_NAME>[TXD0]</PIN_NAME>
<ALT_NAME>[PE1]</ALT_NAME>
<DESCRIPTION/>
</PIN3>
<PIN4>
<PIN_NAME>[XCK:AIN0]</PIN_NAME>
<ALT_NAME>[PE2]</ALT_NAME>
<DESCRIPTION/>
</PIN4>
<PIN5>
<PIN_NAME>[OC3A:AIN1]</PIN_NAME>
<ALT_NAME>[PE3]</ALT_NAME>
<DESCRIPTION/>
</PIN5>
<PIN6>
<PIN_NAME>[OC3B:INT4]</PIN_NAME>
<ALT_NAME>[PE4]</ALT_NAME>
<DESCRIPTION/>
</PIN6>
<PIN7>
<PIN_NAME>[OC3C:INT5]</PIN_NAME>
<ALT_NAME>[PE5</ALT_NAME>
<DESCRIPTION/>
</PIN7>
<PIN8>
<PIN_NAME>[T3:INT6]</PIN_NAME>
<ALT_NAME>[PE6]</ALT_NAME>
<DESCRIPTION/>
</PIN8>
<PIN9>
<PIN_NAME>[CLKO:ICP3:INT7]</PIN_NAME>
<ALT_NAME>[PE7]</ALT_NAME>
<DESCRIPTION/>
</PIN9>
<PIN10>
<PIN_NAME>[VCC]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN10>
<PIN11>
<PIN_NAME>[GND]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN11>
<PIN12>
<PIN_NAME>[RXD2]</PIN_NAME>
<ALT_NAME>[PH0]</ALT_NAME>
<DESCRIPTION/>
</PIN12>
<PIN13>
<PIN_NAME>[TXD2]</PIN_NAME>
<ALT_NAME>[PH1]</ALT_NAME>
<DESCRIPTION/>
</PIN13>
<PIN14>
<PIN_NAME>[XCK2]</PIN_NAME>
<ALT_NAME>[PH2]</ALT_NAME>
<DESCRIPTION/>
</PIN14>
<PIN15>
<PIN_NAME>[OC4A]</PIN_NAME>
<ALT_NAME>[PH3]</ALT_NAME>
<DESCRIPTION/>
</PIN15>
<PIN16>
<PIN_NAME>[OC4B]</PIN_NAME>
<ALT_NAME>[PH4]</ALT_NAME>
<DESCRIPTION/>
</PIN16>
<PIN17>
<PIN_NAME>[OC4C]</PIN_NAME>
<ALT_NAME>[PH5</ALT_NAME>
<DESCRIPTION/>
</PIN17>
<PIN18>
<PIN_NAME>[OC2B]</PIN_NAME>
<ALT_NAME>[PH6]</ALT_NAME>
<DESCRIPTION/>
</PIN18>
<PIN19>
<PIN_NAME>['SS:PCINT0]</PIN_NAME>
<ALT_NAME>[PB0]</ALT_NAME>
<DESCRIPTION/>
</PIN19>
<PIN20>
<PIN_NAME>[SCK:PCINT1]</PIN_NAME>
<ALT_NAME>[PB1]</ALT_NAME>
<DESCRIPTION/>
</PIN20>
<PIN21>
<PIN_NAME>[MOSI:PCINT2]</PIN_NAME>
<ALT_NAME>[PB2]</ALT_NAME>
<DESCRIPTION/>
</PIN21>
<PIN22>
<PIN_NAME>[MISO:PCINT3]</PIN_NAME>
<ALT_NAME>[PB3]</ALT_NAME>
<DESCRIPTION/>
</PIN22>
<PIN23>
<PIN_NAME>[OC0A:PCINT4]</PIN_NAME>
<ALT_NAME>[PB4]</ALT_NAME>
<DESCRIPTION/>
</PIN23>
<PIN24>
<PIN_NAME>[OC1A:PCINT5]</PIN_NAME>
<ALT_NAME>[PB5</ALT_NAME>
<DESCRIPTION/>
</PIN24>
<PIN25>
<PIN_NAME>[OC1B:PCINT6]</PIN_NAME>
<ALT_NAME>[PB6]</ALT_NAME>
<DESCRIPTION/>
</PIN25>
<PIN26>
<PIN_NAME>[OC0A:OC1C:PCINT7]</PIN_NAME>
<ALT_NAME>[PB7]</ALT_NAME>
<DESCRIPTION/>
</PIN26>
<PIN27>
<PIN_NAME>[T4]</PIN_NAME>
<ALT_NAME>[PH7]</ALT_NAME>
<DESCRIPTION/>
</PIN27>
<PIN28>
<PIN_NAME>[TOSC2]</PIN_NAME>
<ALT_NAME>[PG3]</ALT_NAME>
<DESCRIPTION/>
</PIN28>
<PIN29>
<PIN_NAME>[TOSC1]</PIN_NAME>
<ALT_NAME>[PG4]</ALT_NAME>
<DESCRIPTION/>
</PIN29>
<PIN30>
<PIN_NAME>['RESET]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN30>
<PIN31>
<PIN_NAME>[VCC]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN31>
<PIN32>
<PIN_NAME>[GND]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN32>
<PIN33>
<PIN_NAME>[XTAL2]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN33>
<PIN34>
<PIN_NAME>[XTAL1]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN34>
<PIN35>
<PIN_NAME>[ICP4]</PIN_NAME>
<ALT_NAME>[PL0]</ALT_NAME>
<DESCRIPTION/>
</PIN35>
<PIN36>
<PIN_NAME>[ICP5]</PIN_NAME>
<ALT_NAME>[PL1]</ALT_NAME>
<DESCRIPTION/>
</PIN36>
<PIN37>
<PIN_NAME>[T5]</PIN_NAME>
<ALT_NAME>[PL2]</ALT_NAME>
<DESCRIPTION/>
</PIN37>
<PIN38>
<PIN_NAME>[OC5A]</PIN_NAME>
<ALT_NAME>[PL3]</ALT_NAME>
<DESCRIPTION/>
</PIN38>
<PIN39>
<PIN_NAME>[OC5B]</PIN_NAME>
<ALT_NAME>[PL4]</ALT_NAME>
<DESCRIPTION/>
</PIN39>
<PIN40>
<PIN_NAME>[OC5C]</PIN_NAME>
<ALT_NAME>[PL5</ALT_NAME>
<DESCRIPTION/>
</PIN40>
<PIN41>
<PIN_NAME>[PL6]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN41>
<PIN42>
<PIN_NAME>[PL7]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN42>
<PIN43>
<PIN_NAME>[SCL:INT0]</PIN_NAME>
<ALT_NAME>[PD0]</ALT_NAME>
<DESCRIPTION/>
</PIN43>
<PIN44>
<PIN_NAME>[SDA:INT1]</PIN_NAME>
<ALT_NAME>[PD1]</ALT_NAME>
<DESCRIPTION/>
</PIN44>
<PIN45>
<PIN_NAME>[RXD1:INT2]</PIN_NAME>
<ALT_NAME>[PD2]</ALT_NAME>
<DESCRIPTION/>
</PIN45>
<PIN46>
<PIN_NAME>[TXD1:INT3]</PIN_NAME>
<ALT_NAME>[PD3]</ALT_NAME>
<DESCRIPTION/>
</PIN46>
<PIN47>
<PIN_NAME>[ICP1]</PIN_NAME>
<ALT_NAME>[PD4]</ALT_NAME>
<DESCRIPTION/>
</PIN47>
<PIN48>
<PIN_NAME>[XCK1]</PIN_NAME>
<ALT_NAME>[PD5]</ALT_NAME>
<DESCRIPTION/>
</PIN48>
<PIN49>
<PIN_NAME>[T1]</PIN_NAME>
<ALT_NAME>[PD6]</ALT_NAME>
<DESCRIPTION/>
</PIN49>
<PIN50>
<PIN_NAME>[T0]</PIN_NAME>
<ALT_NAME>[PD7]</ALT_NAME>
<DESCRIPTION/>
</PIN50>
<PIN51>
<PIN_NAME>['WR]</PIN_NAME>
<ALT_NAME>[PG0]</ALT_NAME>
<DESCRIPTION/>
</PIN51>
<PIN52>
<PIN_NAME>['RD]</PIN_NAME>
<ALT_NAME>[PG1]</ALT_NAME>
<DESCRIPTION/>
</PIN52>
<PIN53>
<PIN_NAME>[A8]</PIN_NAME>
<ALT_NAME>[PC0]</ALT_NAME>
<DESCRIPTION/>
</PIN53>
<PIN54>
<PIN_NAME>[A9]</PIN_NAME>
<ALT_NAME>[PC1]</ALT_NAME>
<DESCRIPTION/>
</PIN54>
<PIN55>
<PIN_NAME>[A10]</PIN_NAME>
<ALT_NAME>[PC2]</ALT_NAME>
<DESCRIPTION/>
</PIN55>
<PIN56>
<PIN_NAME>[A11]</PIN_NAME>
<ALT_NAME>[PC3]</ALT_NAME>
<DESCRIPTION/>
</PIN56>
<PIN57>
<PIN_NAME>[A12]</PIN_NAME>
<ALT_NAME>[PC4]</ALT_NAME>
<DESCRIPTION/>
</PIN57>
<PIN58>
<PIN_NAME>[A13]</PIN_NAME>
<ALT_NAME>[PC5]</ALT_NAME>
<DESCRIPTION/>
</PIN58>
<PIN59>
<PIN_NAME>[A14]</PIN_NAME>
<ALT_NAME>[PC6]</ALT_NAME>
<DESCRIPTION/>
</PIN59>
<PIN60>
<PIN_NAME>[A15]</PIN_NAME>
<ALT_NAME>[PC7]</ALT_NAME>
<DESCRIPTION/>
</PIN60>
<PIN61>
<PIN_NAME>[VCC]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN61>
<PIN62>
<PIN_NAME>[GND]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN62>
<PIN63>
<PIN_NAME>[RXD3:PCINT9]</PIN_NAME>
<ALT_NAME>[PJ0]</ALT_NAME>
<DESCRIPTION/>
</PIN63>
<PIN64>
<PIN_NAME>[TXD3:PCINT10]</PIN_NAME>
<ALT_NAME>[PJ1]</ALT_NAME>
<DESCRIPTION/>
</PIN64>
<PIN65>
<PIN_NAME>[XCK3:PCINT11]</PIN_NAME>
<ALT_NAME>[PJ2]</ALT_NAME>
<DESCRIPTION/>
</PIN65>
<PIN66>
<PIN_NAME>[PCINT12]</PIN_NAME>
<ALT_NAME>[PJ3]</ALT_NAME>
<DESCRIPTION/>
</PIN66>
<PIN67>
<PIN_NAME>[PCINT13]</PIN_NAME>
<ALT_NAME>[PJ4]</ALT_NAME>
<DESCRIPTION/>
</PIN67>
<PIN68>
<PIN_NAME>[PCINT14]</PIN_NAME>
<ALT_NAME>[PJ5</ALT_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN68>
<PIN69>
<PIN_NAME>[PCINT15]</PIN_NAME>
<ALT_NAME>[PJ6]</ALT_NAME>
<DESCRIPTION/>
</PIN69>
<PIN70>
<PIN_NAME>[ALE]</PIN_NAME>
<ALT_NAME>[PG2]</ALT_NAME>
<DESCRIPTION/>
</PIN70>
<PIN71>
<PIN_NAME>[AD7]</PIN_NAME>
<ALT_NAME>[PA7]</ALT_NAME>
<DESCRIPTION/>
</PIN71>
<PIN72>
<PIN_NAME>[AD6]</PIN_NAME>
<ALT_NAME>[PA6]</ALT_NAME>
<DESCRIPTION/>
</PIN72>
<PIN73>
<PIN_NAME>[AD5]</PIN_NAME>
<ALT_NAME>[PA5]</ALT_NAME>
<DESCRIPTION/>
</PIN73>
<PIN74>
<PIN_NAME>[AD4]</PIN_NAME>
<ALT_NAME>[PA4]</ALT_NAME>
<DESCRIPTION/>
</PIN74>
<PIN75>
<PIN_NAME>[AD3]</PIN_NAME>
<ALT_NAME>[PA3]</ALT_NAME>
<DESCRIPTION/>
</PIN75>
<PIN76>
<PIN_NAME>[AD2]</PIN_NAME>
<ALT_NAME>[PA2]</ALT_NAME>
<DESCRIPTION/>
</PIN76>
<PIN77>
<PIN_NAME>[AD1]</PIN_NAME>
<ALT_NAME>[PA1]</ALT_NAME>
<DESCRIPTION/>
</PIN77>
<PIN78>
<PIN_NAME>[AD0]</PIN_NAME>
<ALT_NAME>[PA0]</ALT_NAME>
<DESCRIPTION/>
</PIN78>
<PIN79>
<PIN_NAME>[PJ7]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN79>
<PIN80>
<PIN_NAME>[VCC]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN80>
<PIN81>
<PIN_NAME>[GND]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN81>
<PIN82>
<PIN_NAME>[ADC15:PCINT23]</PIN_NAME>
<ALT_NAME>[PK7]</ALT_NAME>
<DESCRIPTION/>
</PIN82>
<PIN83>
<PIN_NAME>[ADC14:PCINT22]</PIN_NAME>
<ALT_NAME>[PK6]</ALT_NAME>
<DESCRIPTION/>
</PIN83>
<PIN84>
<PIN_NAME>[ADC13:PCINT21]</PIN_NAME>
<ALT_NAME>[PK5]</ALT_NAME>
<DESCRIPTION/>
</PIN84>
<PIN85>
<PIN_NAME>[ADC12:PCINT20]</PIN_NAME>
<ALT_NAME>[PK4]</ALT_NAME>
<DESCRIPTION/>
</PIN85>
<PIN86>
<PIN_NAME>[ADC11:PCINT19]</PIN_NAME>
<ALT_NAME>[PK3]</ALT_NAME>
<DESCRIPTION/>
</PIN86>
<PIN87>
<PIN_NAME>[ADC10:PCINT18]</PIN_NAME>
<ALT_NAME>[PK2]</ALT_NAME>
<DESCRIPTION/>
</PIN87>
<PIN88>
<PIN_NAME>[ADC9:PCINT17]</PIN_NAME>
<ALT_NAME>[PK1]</ALT_NAME>
<DESCRIPTION/>
</PIN88>
<PIN89>
<PIN_NAME>[ADC8:PCINT16]</PIN_NAME>
<ALT_NAME>[PK0]</ALT_NAME>
<DESCRIPTION/>
</PIN89>
<PIN90>
<PIN_NAME>[ADC7:TDI]</PIN_NAME>
<ALT_NAME>[PF7]</ALT_NAME>
<DESCRIPTION/>
</PIN90>
<PIN91>
<PIN_NAME>[ADC6:TDO]</PIN_NAME>
<ALT_NAME>[PF6]</ALT_NAME>
<DESCRIPTION/>
</PIN91>
<PIN92>
<PIN_NAME>[ADC5:TMS]</PIN_NAME>
<ALT_NAME>[PF5</ALT_NAME>
<DESCRIPTION/>
</PIN92>
<PIN93>
<PIN_NAME>[ADC4:TCK]</PIN_NAME>
<ALT_NAME>[PF4]</ALT_NAME>
<DESCRIPTION/>
</PIN93>
<PIN94>
<PIN_NAME>[ADC3]</PIN_NAME>
<ALT_NAME>[PF3]</ALT_NAME>
<DESCRIPTION/>
</PIN94>
<PIN95>
<PIN_NAME>[ADC2]</PIN_NAME>
<ALT_NAME>[PF2]</ALT_NAME>
<DESCRIPTION/>
</PIN95>
<PIN96>
<PIN_NAME>[ADC1]</PIN_NAME>
<ALT_NAME>[PF1]</ALT_NAME>
<DESCRIPTION/>
</PIN96>
<PIN97>
<PIN_NAME>[ADC0]</PIN_NAME>
<ALT_NAME>[PF0]</ALT_NAME>
<DESCRIPTION/>
</PIN97>
<PIN98>
<PIN_NAME>[AREF]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN98>
<PIN99>
<PIN_NAME>[AGND]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN99>
<PIN100>
<PIN_NAME>[AVCC]</PIN_NAME>
<ALT_NAME/>
<DESCRIPTION/>
</PIN100>
</TQFP>
</PACKAGE>
<ADMIN>
<PART_NAME>ATmega640</PART_NAME>
<SPEED>16MHZ</SPEED>
<BUILD>1</BUILD>
<RELEASE_STATUS>RELEASED</RELEASE_STATUS>
<SIGNATURE>
<ADDR000>$1E</ADDR000>
<ADDR001>$96</ADDR001>
<ADDR002>$08</ADDR002>
</SIGNATURE>
</ADMIN>
<MEMORY>
<ID>AVRSimMemory8bit.SimMemory8bit</ID>
<PROG_FLASH>65536</PROG_FLASH>
<EEPROM>4096</EEPROM>
<INT_SRAM>
<SIZE>8192</SIZE>
<START_ADDR>$200</START_ADDR>
</INT_SRAM>
<EXT_SRAM>
<SIZE>65536</SIZE>
<START_ADDR>$2200</START_ADDR>
</EXT_SRAM>
<IO_MEMORY>
<IO_START_ADDR>$00</IO_START_ADDR>
<IO_STOP_ADDR>$3F</IO_STOP_ADDR>
<EXT_IO_START_ADDR>$60</EXT_IO_START_ADDR>
<EXT_IO_STOP_ADDR>$1FF</EXT_IO_STOP_ADDR>
<MEM_START_ADDR>$20</MEM_START_ADDR>
<MEM_STOP_ADDR>$1FF</MEM_STOP_ADDR>
<UDR3>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$136</MEM_ADDR>
<UDR3-0_MASK>0x01</UDR3-0_MASK><UDR3-1_MASK>0x02</UDR3-1_MASK><UDR3-2_MASK>0x04</UDR3-2_MASK><UDR3-3_MASK>0x08</UDR3-3_MASK><UDR3-4_MASK>0x10</UDR3-4_MASK><UDR3-5_MASK>0x20</UDR3-5_MASK><UDR3-6_MASK>0x40</UDR3-6_MASK><UDR3-7_MASK>0x80</UDR3-7_MASK></UDR3>
<UBRR3H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$135</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRR3H>
<UBRR3L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$134</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR3L>
<UCSR3C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$132</MEM_ADDR>
<UCPOL3_MASK>0x01</UCPOL3_MASK><UCSZ30_MASK>0x02</UCSZ30_MASK><UCSZ31_MASK>0x04</UCSZ31_MASK><USBS3_MASK>0x08</USBS3_MASK><UPM30_MASK>0x10</UPM30_MASK><UPM31_MASK>0x20</UPM31_MASK><UMSEL30_MASK>0x40</UMSEL30_MASK><UMSEL31_MASK>0x80</UMSEL31_MASK></UCSR3C>
<UCSR3B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$131</MEM_ADDR>
<TXB83_MASK>0x01</TXB83_MASK><RXB83_MASK>0x02</RXB83_MASK><UCSZ32_MASK>0x04</UCSZ32_MASK><TXEN3_MASK>0x08</TXEN3_MASK><RXEN3_MASK>0x10</RXEN3_MASK><UDRIE3_MASK>0x20</UDRIE3_MASK><TXCIE3_MASK>0x40</TXCIE3_MASK><RXCIE3_MASK>0x80</RXCIE3_MASK></UCSR3B>
<UCSR3A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$130</MEM_ADDR>
<MPCM3_MASK>0x01</MPCM3_MASK><U2X3_MASK>0x02</U2X3_MASK><UPE3_MASK>0x04</UPE3_MASK><DOR3_MASK>0x08</DOR3_MASK><FE3_MASK>0x10</FE3_MASK><UDRE3_MASK>0x20</UDRE3_MASK><TXC3_MASK>0x40</TXC3_MASK><RXC3_MASK>0x80</RXC3_MASK></UCSR3A>
<OCR5CH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12D</MEM_ADDR>
<OCR5CH0_MASK>0x01</OCR5CH0_MASK><OCR5CH1_MASK>0x02</OCR5CH1_MASK><OCR5CH2_MASK>0x04</OCR5CH2_MASK><OCR5CH3_MASK>0x08</OCR5CH3_MASK><OCR5CH4_MASK>0x10</OCR5CH4_MASK><OCR5CH5_MASK>0x20</OCR5CH5_MASK><OCR5CH6_MASK>0x40</OCR5CH6_MASK><OCR5CH7_MASK>0x80</OCR5CH7_MASK></OCR5CH>
<OCR5CL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12C</MEM_ADDR>
<OCR5CL0_MASK>0x01</OCR5CL0_MASK><OCR5CL1_MASK>0x02</OCR5CL1_MASK><OCR5CL2_MASK>0x04</OCR5CL2_MASK><OCR5CL3_MASK>0x08</OCR5CL3_MASK><OCR5CL4_MASK>0x10</OCR5CL4_MASK><OCR5CL5_MASK>0x20</OCR5CL5_MASK><OCR5CL6_MASK>0x40</OCR5CL6_MASK><OCR5CL7_MASK>0x80</OCR5CL7_MASK></OCR5CL>
<OCR5BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12B</MEM_ADDR>
<OCR5BH0_MASK>0x01</OCR5BH0_MASK><OCR5BH1_MASK>0x02</OCR5BH1_MASK><OCR5BH2_MASK>0x04</OCR5BH2_MASK><OCR5BH3_MASK>0x08</OCR5BH3_MASK><OCR5BH4_MASK>0x10</OCR5BH4_MASK><OCR5BH5_MASK>0x20</OCR5BH5_MASK><OCR5BH6_MASK>0x40</OCR5BH6_MASK><OCR5BH7_MASK>0x80</OCR5BH7_MASK></OCR5BH>
<OCR5BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12A</MEM_ADDR>
<OCR5BL0_MASK>0x01</OCR5BL0_MASK><OCR5BL1_MASK>0x02</OCR5BL1_MASK><OCR5BL2_MASK>0x04</OCR5BL2_MASK><OCR5BL3_MASK>0x08</OCR5BL3_MASK><OCR5BL4_MASK>0x10</OCR5BL4_MASK><OCR5BL5_MASK>0x20</OCR5BL5_MASK><OCR5BL6_MASK>0x40</OCR5BL6_MASK><OCR5BL7_MASK>0x80</OCR5BL7_MASK></OCR5BL>
<OCR5AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$129</MEM_ADDR>
<OCR5AH0_MASK>0x01</OCR5AH0_MASK><OCR5AH1_MASK>0x02</OCR5AH1_MASK><OCR5AH2_MASK>0x04</OCR5AH2_MASK><OCR5AH3_MASK>0x08</OCR5AH3_MASK><OCR5AH4_MASK>0x10</OCR5AH4_MASK><OCR5AH5_MASK>0x20</OCR5AH5_MASK><OCR5AH6_MASK>0x40</OCR5AH6_MASK><OCR5AH7_MASK>0x80</OCR5AH7_MASK></OCR5AH>
<OCR5AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$128</MEM_ADDR>
<OCR5AL0_MASK>0x01</OCR5AL0_MASK><OCR5AL1_MASK>0x02</OCR5AL1_MASK><OCR5AL2_MASK>0x04</OCR5AL2_MASK><OCR5AL3_MASK>0x08</OCR5AL3_MASK><OCR5AL4_MASK>0x10</OCR5AL4_MASK><OCR5AL5_MASK>0x20</OCR5AL5_MASK><OCR5AL6_MASK>0x40</OCR5AL6_MASK><OCR5AL7_MASK>0x80</OCR5AL7_MASK></OCR5AL>
<ICR5H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$127</MEM_ADDR>
<ICR5H0_MASK>0x01</ICR5H0_MASK><ICR5H1_MASK>0x02</ICR5H1_MASK><ICR5H2_MASK>0x04</ICR5H2_MASK><ICR5H3_MASK>0x08</ICR5H3_MASK><ICR5H4_MASK>0x10</ICR5H4_MASK><ICR5H5_MASK>0x20</ICR5H5_MASK><ICR5H6_MASK>0x40</ICR5H6_MASK><ICR5H7_MASK>0x80</ICR5H7_MASK></ICR5H>
<ICR5L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$126</MEM_ADDR>
<ICR5L0_MASK>0x01</ICR5L0_MASK><ICR5L1_MASK>0x02</ICR5L1_MASK><ICR5L2_MASK>0x04</ICR5L2_MASK><ICR5L3_MASK>0x08</ICR5L3_MASK><ICR5L4_MASK>0x10</ICR5L4_MASK><ICR5L5_MASK>0x20</ICR5L5_MASK><ICR5L6_MASK>0x40</ICR5L6_MASK><ICR5L7_MASK>0x80</ICR5L7_MASK></ICR5L>
<TCNT5H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$125</MEM_ADDR>
<TCNT5H0_MASK>0x01</TCNT5H0_MASK><TCNT5H1_MASK>0x02</TCNT5H1_MASK><TCNT5H2_MASK>0x04</TCNT5H2_MASK><TCNT5H3_MASK>0x08</TCNT5H3_MASK><TCNT5H4_MASK>0x10</TCNT5H4_MASK><TCNT5H5_MASK>0x20</TCNT5H5_MASK><TCNT5H6_MASK>0x40</TCNT5H6_MASK><TCNT5H7_MASK>0x80</TCNT5H7_MASK></TCNT5H>
<TCNT5L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$124</MEM_ADDR>
<TCNT5L0_MASK>0x01</TCNT5L0_MASK><TCNT5L1_MASK>0x02</TCNT5L1_MASK><TCNT5L2_MASK>0x04</TCNT5L2_MASK><TCNT5L3_MASK>0x08</TCNT5L3_MASK><TCNT5L4_MASK>0x10</TCNT5L4_MASK><TCNT5L5_MASK>0x20</TCNT5L5_MASK><TCNT5L6_MASK>0x40</TCNT5L6_MASK><TCNT5L7_MASK>0x80</TCNT5L7_MASK></TCNT5L>
<TCCR5C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$122</MEM_ADDR>
<FOC5C_MASK>0x20</FOC5C_MASK><FOC5B_MASK>0x40</FOC5B_MASK><FOC5A_MASK>0x80</FOC5A_MASK></TCCR5C>
<TCCR5B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$121</MEM_ADDR>
<CS50_MASK>0x01</CS50_MASK><CS51_MASK>0x02</CS51_MASK><CS52_MASK>0x04</CS52_MASK><WGM52_MASK>0x08</WGM52_MASK><WGM53_MASK>0x10</WGM53_MASK><ICES5_MASK>0x40</ICES5_MASK><ICNC5_MASK>0x80</ICNC5_MASK></TCCR5B>
<TCCR5A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$120</MEM_ADDR>
<WGM50_MASK>0x01</WGM50_MASK><WGM51_MASK>0x02</WGM51_MASK><COM5C0_MASK>0x04</COM5C0_MASK><COM5C1_MASK>0x08</COM5C1_MASK><COM5B0_MASK>0x10</COM5B0_MASK><COM5B1_MASK>0x20</COM5B1_MASK><COM5A0_MASK>0x40</COM5A0_MASK><COM5A1_MASK>0x80</COM5A1_MASK></TCCR5A>
<PORTL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$10B</MEM_ADDR>
<PORTL0_MASK>0x01</PORTL0_MASK><PORTL1_MASK>0x02</PORTL1_MASK><PORTL2_MASK>0x04</PORTL2_MASK><PORTL3_MASK>0x08</PORTL3_MASK><PORTL4_MASK>0x10</PORTL4_MASK><PORTL5_MASK>0x20</PORTL5_MASK><PORTL6_MASK>0x40</PORTL6_MASK><PORTL7_MASK>0x80</PORTL7_MASK></PORTL>
<DDRL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$10A</MEM_ADDR>
<DDL0_MASK>0x01</DDL0_MASK><DDL1_MASK>0x02</DDL1_MASK><DDL2_MASK>0x04</DDL2_MASK><DDL3_MASK>0x08</DDL3_MASK><DDL4_MASK>0x10</DDL4_MASK><DDL5_MASK>0x20</DDL5_MASK><DDL6_MASK>0x40</DDL6_MASK><DDL7_MASK>0x80</DDL7_MASK></DDRL>
<PINL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$109</MEM_ADDR>
<PINL0_MASK>0x01</PINL0_MASK><PINL1_MASK>0x02</PINL1_MASK><PINL2_MASK>0x04</PINL2_MASK><PINL3_MASK>0x08</PINL3_MASK><PINL4_MASK>0x10</PINL4_MASK><PINL5_MASK>0x20</PINL5_MASK><PINL6_MASK>0x40</PINL6_MASK><PINL7_MASK>0x80</PINL7_MASK></PINL>
<PORTK>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$108</MEM_ADDR>
<PORTK0_MASK>0x01</PORTK0_MASK><PORTK1_MASK>0x02</PORTK1_MASK><PORTK2_MASK>0x04</PORTK2_MASK><PORTK3_MASK>0x08</PORTK3_MASK><PORTK4_MASK>0x10</PORTK4_MASK><PORTK5_MASK>0x20</PORTK5_MASK><PORTK6_MASK>0x40</PORTK6_MASK><PORTK7_MASK>0x80</PORTK7_MASK></PORTK>
<DDRK>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$107</MEM_ADDR>
<DDK0_MASK>0x01</DDK0_MASK><DDK1_MASK>0x02</DDK1_MASK><DDK2_MASK>0x04</DDK2_MASK><DDK3_MASK>0x08</DDK3_MASK><DDK4_MASK>0x10</DDK4_MASK><DDK5_MASK>0x20</DDK5_MASK><DDK6_MASK>0x40</DDK6_MASK><DDK7_MASK>0x80</DDK7_MASK></DDRK>
<PINK>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$106</MEM_ADDR>
<PINK0_MASK>0x01</PINK0_MASK><PINK1_MASK>0x02</PINK1_MASK><PINK2_MASK>0x04</PINK2_MASK><PINK3_MASK>0x08</PINK3_MASK><PINK4_MASK>0x10</PINK4_MASK><PINK5_MASK>0x20</PINK5_MASK><PINK6_MASK>0x40</PINK6_MASK><PINK7_MASK>0x80</PINK7_MASK></PINK>
<PORTJ>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$105</MEM_ADDR>
<PORTJ0_MASK>0x01</PORTJ0_MASK><PORTJ1_MASK>0x02</PORTJ1_MASK><PORTJ2_MASK>0x04</PORTJ2_MASK><PORTJ3_MASK>0x08</PORTJ3_MASK><PORTJ4_MASK>0x10</PORTJ4_MASK><PORTJ5_MASK>0x20</PORTJ5_MASK><PORTJ6_MASK>0x40</PORTJ6_MASK><PORTJ7_MASK>0x80</PORTJ7_MASK></PORTJ>
<DDRJ>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$104</MEM_ADDR>
<DDJ0_MASK>0x01</DDJ0_MASK><DDJ1_MASK>0x02</DDJ1_MASK><DDJ2_MASK>0x04</DDJ2_MASK><DDJ3_MASK>0x08</DDJ3_MASK><DDJ4_MASK>0x10</DDJ4_MASK><DDJ5_MASK>0x20</DDJ5_MASK><DDJ6_MASK>0x40</DDJ6_MASK><DDJ7_MASK>0x80</DDJ7_MASK></DDRJ>
<PINJ>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$103</MEM_ADDR>
<PINJ0_MASK>0x01</PINJ0_MASK><PINJ1_MASK>0x02</PINJ1_MASK><PINJ2_MASK>0x04</PINJ2_MASK><PINJ3_MASK>0x08</PINJ3_MASK><PINJ4_MASK>0x10</PINJ4_MASK><PINJ5_MASK>0x20</PINJ5_MASK><PINJ6_MASK>0x40</PINJ6_MASK><PINJ7_MASK>0x80</PINJ7_MASK></PINJ>
<PORTH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$102</MEM_ADDR>
<PORTH0_MASK>0x01</PORTH0_MASK><PORTH1_MASK>0x02</PORTH1_MASK><PORTH2_MASK>0x04</PORTH2_MASK><PORTH3_MASK>0x08</PORTH3_MASK><PORTH4_MASK>0x10</PORTH4_MASK><PORTH5_MASK>0x20</PORTH5_MASK><PORTH6_MASK>0x40</PORTH6_MASK><PORTH7_MASK>0x80</PORTH7_MASK></PORTH>
<DDRH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$101</MEM_ADDR>
<DDH0_MASK>0x01</DDH0_MASK><DDH1_MASK>0x02</DDH1_MASK><DDH2_MASK>0x04</DDH2_MASK><DDH3_MASK>0x08</DDH3_MASK><DDH4_MASK>0x10</DDH4_MASK><DDH5_MASK>0x20</DDH5_MASK><DDH6_MASK>0x40</DDH6_MASK><DDH7_MASK>0x80</DDH7_MASK></DDRH>
<PINH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$100</MEM_ADDR>
<PINH0_MASK>0x01</PINH0_MASK><PINH1_MASK>0x02</PINH1_MASK><PINH2_MASK>0x04</PINH2_MASK><PINH3_MASK>0x08</PINH3_MASK><PINH4_MASK>0x10</PINH4_MASK><PINH5_MASK>0x20</PINH5_MASK><PINH6_MASK>0x40</PINH6_MASK><PINH7_MASK>0x80</PINH7_MASK></PINH>
<UDR2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D6</MEM_ADDR>
<UDR2-0_MASK>0x01</UDR2-0_MASK><UDR2-1_MASK>0x02</UDR2-1_MASK><UDR2-2_MASK>0x04</UDR2-2_MASK><UDR2-3_MASK>0x08</UDR2-3_MASK><UDR2-4_MASK>0x10</UDR2-4_MASK><UDR2-5_MASK>0x20</UDR2-5_MASK><UDR2-6_MASK>0x40</UDR2-6_MASK><UDR2-7_MASK>0x80</UDR2-7_MASK></UDR2>
<UBRR2H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D5</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRR2H>
<UBRR2L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D4</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR2L>
<UCSR2C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D2</MEM_ADDR>
<UCPOL2_MASK>0x01</UCPOL2_MASK><UCSZ20_MASK>0x02</UCSZ20_MASK><UCSZ21_MASK>0x04</UCSZ21_MASK><USBS2_MASK>0x08</USBS2_MASK><UPM20_MASK>0x10</UPM20_MASK><UPM21_MASK>0x20</UPM21_MASK><UMSEL20_MASK>0x40</UMSEL20_MASK><UMSEL21_MASK>0x80</UMSEL21_MASK></UCSR2C>
<UCSR2B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D1</MEM_ADDR>
<TXB82_MASK>0x01</TXB82_MASK><RXB82_MASK>0x02</RXB82_MASK><UCSZ22_MASK>0x04</UCSZ22_MASK><TXEN2_MASK>0x08</TXEN2_MASK><RXEN2_MASK>0x10</RXEN2_MASK><UDRIE2_MASK>0x20</UDRIE2_MASK><TXCIE2_MASK>0x40</TXCIE2_MASK><RXCIE2_MASK>0x80</RXCIE2_MASK></UCSR2B>
<UCSR2A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D0</MEM_ADDR>
<MPCM2_MASK>0x01</MPCM2_MASK><U2X2_MASK>0x02</U2X2_MASK><UPE2_MASK>0x04</UPE2_MASK><DOR2_MASK>0x08</DOR2_MASK><FE2_MASK>0x10</FE2_MASK><UDRE2_MASK>0x20</UDRE2_MASK><TXC2_MASK>0x40</TXC2_MASK><RXC2_MASK>0x80</RXC2_MASK></UCSR2A>
<UDR1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CE</MEM_ADDR>
<UDR1-0_MASK>0x01</UDR1-0_MASK><UDR1-1_MASK>0x02</UDR1-1_MASK><UDR1-2_MASK>0x04</UDR1-2_MASK><UDR1-3_MASK>0x08</UDR1-3_MASK><UDR1-4_MASK>0x10</UDR1-4_MASK><UDR1-5_MASK>0x20</UDR1-5_MASK><UDR1-6_MASK>0x40</UDR1-6_MASK><UDR1-7_MASK>0x80</UDR1-7_MASK></UDR1>
<UBRR1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CD</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRR1H>
<UBRR1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CC</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR1L>
<UCSR1C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CA</MEM_ADDR>
<UCPOL1_MASK>0x01</UCPOL1_MASK><UCSZ10_MASK>0x02</UCSZ10_MASK><UCSZ11_MASK>0x04</UCSZ11_MASK><USBS1_MASK>0x08</USBS1_MASK><UPM10_MASK>0x10</UPM10_MASK><UPM11_MASK>0x20</UPM11_MASK><UMSEL10_MASK>0x40</UMSEL10_MASK><UMSEL11_MASK>0x80</UMSEL11_MASK></UCSR1C>
<UCSR1B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C9</MEM_ADDR>
<TXB81_MASK>0x01</TXB81_MASK><RXB81_MASK>0x02</RXB81_MASK><UCSZ12_MASK>0x04</UCSZ12_MASK><TXEN1_MASK>0x08</TXEN1_MASK><RXEN1_MASK>0x10</RXEN1_MASK><UDRIE1_MASK>0x20</UDRIE1_MASK><TXCIE1_MASK>0x40</TXCIE1_MASK><RXCIE1_MASK>0x80</RXCIE1_MASK></UCSR1B>
<UCSR1A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C8</MEM_ADDR>
<MPCM1_MASK>0x01</MPCM1_MASK><U2X1_MASK>0x02</U2X1_MASK><UPE1_MASK>0x04</UPE1_MASK><DOR1_MASK>0x08</DOR1_MASK><FE1_MASK>0x10</FE1_MASK><UDRE1_MASK>0x20</UDRE1_MASK><TXC1_MASK>0x40</TXC1_MASK><RXC1_MASK>0x80</RXC1_MASK></UCSR1A>
<UDR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C6</MEM_ADDR>
<UDR0-0_MASK>0x01</UDR0-0_MASK><UDR0-1_MASK>0x02</UDR0-1_MASK><UDR0-2_MASK>0x04</UDR0-2_MASK><UDR0-3_MASK>0x08</UDR0-3_MASK><UDR0-4_MASK>0x10</UDR0-4_MASK><UDR0-5_MASK>0x20</UDR0-5_MASK><UDR0-6_MASK>0x40</UDR0-6_MASK><UDR0-7_MASK>0x80</UDR0-7_MASK></UDR0>
<UBRR0H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C5</MEM_ADDR>
<UBRR8_MASK>0x01</UBRR8_MASK><UBRR9_MASK>0x02</UBRR9_MASK><UBRR10_MASK>0x04</UBRR10_MASK><UBRR11_MASK>0x08</UBRR11_MASK></UBRR0H>
<UBRR0L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C4</MEM_ADDR>
<UBRR0_MASK>0x01</UBRR0_MASK><UBRR1_MASK>0x02</UBRR1_MASK><UBRR2_MASK>0x04</UBRR2_MASK><UBRR3_MASK>0x08</UBRR3_MASK><UBRR4_MASK>0x10</UBRR4_MASK><UBRR5_MASK>0x20</UBRR5_MASK><UBRR6_MASK>0x40</UBRR6_MASK><UBRR7_MASK>0x80</UBRR7_MASK></UBRR0L>
<UCSR0C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C2</MEM_ADDR>
<UCPOL0_MASK>0x01</UCPOL0_MASK><UCSZ00_MASK>0x02</UCSZ00_MASK><UCSZ01_MASK>0x04</UCSZ01_MASK><USBS0_MASK>0x08</USBS0_MASK><UPM00_MASK>0x10</UPM00_MASK><UPM01_MASK>0x20</UPM01_MASK><UMSEL00_MASK>0x40</UMSEL00_MASK><UMSEL01_MASK>0x80</UMSEL01_MASK></UCSR0C>
<UCSR0B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C1</MEM_ADDR>
<TXB80_MASK>0x01</TXB80_MASK><RXB80_MASK>0x02</RXB80_MASK><UCSZ02_MASK>0x04</UCSZ02_MASK><TXEN0_MASK>0x08</TXEN0_MASK><RXEN0_MASK>0x10</RXEN0_MASK><UDRIE0_MASK>0x20</UDRIE0_MASK><TXCIE0_MASK>0x40</TXCIE0_MASK><RXCIE0_MASK>0x80</RXCIE0_MASK></UCSR0B>
<UCSR0A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C0</MEM_ADDR>
<MPCM0_MASK>0x01</MPCM0_MASK><U2X0_MASK>0x02</U2X0_MASK><UPE0_MASK>0x04</UPE0_MASK><DOR0_MASK>0x08</DOR0_MASK><FE0_MASK>0x10</FE0_MASK><UDRE0_MASK>0x20</UDRE0_MASK><TXC0_MASK>0x40</TXC0_MASK><RXC0_MASK>0x80</RXC0_MASK></UCSR0A>
<TWAMR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BD</MEM_ADDR>
<TWAM0_MASK>0x02</TWAM0_MASK><TWAM1_MASK>0x04</TWAM1_MASK><TWAM2_MASK>0x08</TWAM2_MASK><TWAM3_MASK>0x10</TWAM3_MASK><TWAM4_MASK>0x20</TWAM4_MASK><TWAM5_MASK>0x40</TWAM5_MASK><TWAM6_MASK>0x80</TWAM6_MASK></TWAMR>
<TWCR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BC</MEM_ADDR>
<TWIE_MASK>0x01</TWIE_MASK><TWEN_MASK>0x04</TWEN_MASK><TWWC_MASK>0x08</TWWC_MASK><TWSTO_MASK>0x10</TWSTO_MASK><TWSTA_MASK>0x20</TWSTA_MASK><TWEA_MASK>0x40</TWEA_MASK><TWINT_MASK>0x80</TWINT_MASK></TWCR>
<TWDR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BB</MEM_ADDR>
<TWD0_MASK>0x01</TWD0_MASK><TWD1_MASK>0x02</TWD1_MASK><TWD2_MASK>0x04</TWD2_MASK><TWD3_MASK>0x08</TWD3_MASK><TWD4_MASK>0x10</TWD4_MASK><TWD5_MASK>0x20</TWD5_MASK><TWD6_MASK>0x40</TWD6_MASK><TWD7_MASK>0x80</TWD7_MASK></TWDR>
<TWAR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BA</MEM_ADDR>
<TWGCE_MASK>0x01</TWGCE_MASK><TWA0_MASK>0x02</TWA0_MASK><TWA1_MASK>0x04</TWA1_MASK><TWA2_MASK>0x08</TWA2_MASK><TWA3_MASK>0x10</TWA3_MASK><TWA4_MASK>0x20</TWA4_MASK><TWA5_MASK>0x40</TWA5_MASK><TWA6_MASK>0x80</TWA6_MASK></TWAR>
<TWSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B9</MEM_ADDR>
<TWPS0_MASK>0x01</TWPS0_MASK><TWPS1_MASK>0x02</TWPS1_MASK><TWS3_MASK>0x08</TWS3_MASK><TWS4_MASK>0x10</TWS4_MASK><TWS5_MASK>0x20</TWS5_MASK><TWS6_MASK>0x40</TWS6_MASK><TWS7_MASK>0x80</TWS7_MASK></TWSR>
<TWBR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B8</MEM_ADDR>
<TWBR0_MASK>0x01</TWBR0_MASK><TWBR1_MASK>0x02</TWBR1_MASK><TWBR2_MASK>0x04</TWBR2_MASK><TWBR3_MASK>0x08</TWBR3_MASK><TWBR4_MASK>0x10</TWBR4_MASK><TWBR5_MASK>0x20</TWBR5_MASK><TWBR6_MASK>0x40</TWBR6_MASK><TWBR7_MASK>0x80</TWBR7_MASK></TWBR>
<ASSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B6</MEM_ADDR>
<TCR2BUB_MASK>0x01</TCR2BUB_MASK><TCR2AUB_MASK>0x02</TCR2AUB_MASK><OCR2BUB_MASK>0x04</OCR2BUB_MASK><OCR2AUB_MASK>0x08</OCR2AUB_MASK><TCN2UB_MASK>0x10</TCN2UB_MASK><AS2_MASK>0x20</AS2_MASK><EXCLK_MASK>0x40</EXCLK_MASK></ASSR>
<OCR2B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B4</MEM_ADDR>
<OCR2-0_MASK>0x01</OCR2-0_MASK><OCR2-1_MASK>0x02</OCR2-1_MASK><OCR2-2_MASK>0x04</OCR2-2_MASK><OCR2-3_MASK>0x08</OCR2-3_MASK><OCR2-4_MASK>0x10</OCR2-4_MASK><OCR2-5_MASK>0x20</OCR2-5_MASK><OCR2-6_MASK>0x40</OCR2-6_MASK><OCR2-7_MASK>0x80</OCR2-7_MASK></OCR2B>
<OCR2A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B3</MEM_ADDR>
<OCR2-0_MASK>0x01</OCR2-0_MASK><OCR2-1_MASK>0x02</OCR2-1_MASK><OCR2-2_MASK>0x04</OCR2-2_MASK><OCR2-3_MASK>0x08</OCR2-3_MASK><OCR2-4_MASK>0x10</OCR2-4_MASK><OCR2-5_MASK>0x20</OCR2-5_MASK><OCR2-6_MASK>0x40</OCR2-6_MASK><OCR2-7_MASK>0x80</OCR2-7_MASK></OCR2A>
<TCNT2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B2</MEM_ADDR>
<TCNT2-0_MASK>0x01</TCNT2-0_MASK><TCNT2-1_MASK>0x02</TCNT2-1_MASK><TCNT2-2_MASK>0x04</TCNT2-2_MASK><TCNT2-3_MASK>0x08</TCNT2-3_MASK><TCNT2-4_MASK>0x10</TCNT2-4_MASK><TCNT2-5_MASK>0x20</TCNT2-5_MASK><TCNT2-6_MASK>0x40</TCNT2-6_MASK><TCNT2-7_MASK>0x80</TCNT2-7_MASK></TCNT2>
<TCCR2B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B1</MEM_ADDR>
<CS20_MASK>0x01</CS20_MASK><CS21_MASK>0x02</CS21_MASK><CS22_MASK>0x04</CS22_MASK><WGM22_MASK>0x08</WGM22_MASK><FOC2B_MASK>0x40</FOC2B_MASK><FOC2A_MASK>0x80</FOC2A_MASK></TCCR2B>
<TCCR2A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B0</MEM_ADDR>
<WGM20_MASK>0x01</WGM20_MASK><WGM21_MASK>0x02</WGM21_MASK><COM2B0_MASK>0x10</COM2B0_MASK><COM2B1_MASK>0x20</COM2B1_MASK><COM2A0_MASK>0x40</COM2A0_MASK><COM2A1_MASK>0x80</COM2A1_MASK></TCCR2A>
<OCR4CH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AD</MEM_ADDR>
<OCR4CH0_MASK>0x01</OCR4CH0_MASK><OCR4CH1_MASK>0x02</OCR4CH1_MASK><OCR4CH2_MASK>0x04</OCR4CH2_MASK><OCR4CH3_MASK>0x08</OCR4CH3_MASK><OCR4CH4_MASK>0x10</OCR4CH4_MASK><OCR4CH5_MASK>0x20</OCR4CH5_MASK><OCR4CH6_MASK>0x40</OCR4CH6_MASK><OCR4CH7_MASK>0x80</OCR4CH7_MASK></OCR4CH>
<OCR4CL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AC</MEM_ADDR>
<OCR4CL0_MASK>0x01</OCR4CL0_MASK><OCR4CL1_MASK>0x02</OCR4CL1_MASK><OCR4CL2_MASK>0x04</OCR4CL2_MASK><OCR4CL3_MASK>0x08</OCR4CL3_MASK><OCR4CL4_MASK>0x10</OCR4CL4_MASK><OCR4CL5_MASK>0x20</OCR4CL5_MASK><OCR4CL6_MASK>0x40</OCR4CL6_MASK><OCR4CL7_MASK>0x80</OCR4CL7_MASK></OCR4CL>
<OCR4BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AB</MEM_ADDR>
<OCR4BH0_MASK>0x01</OCR4BH0_MASK><OCR4BH1_MASK>0x02</OCR4BH1_MASK><OCR4BH2_MASK>0x04</OCR4BH2_MASK><OCR4BH3_MASK>0x08</OCR4BH3_MASK><OCR4BH4_MASK>0x10</OCR4BH4_MASK><OCR4BH5_MASK>0x20</OCR4BH5_MASK><OCR4BH6_MASK>0x40</OCR4BH6_MASK><OCR4BH7_MASK>0x80</OCR4BH7_MASK></OCR4BH>
<OCR4BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AA</MEM_ADDR>
<OCR4BL0_MASK>0x01</OCR4BL0_MASK><OCR4BL1_MASK>0x02</OCR4BL1_MASK><OCR4BL2_MASK>0x04</OCR4BL2_MASK><OCR4BL3_MASK>0x08</OCR4BL3_MASK><OCR4BL4_MASK>0x10</OCR4BL4_MASK><OCR4BL5_MASK>0x20</OCR4BL5_MASK><OCR4BL6_MASK>0x40</OCR4BL6_MASK><OCR4BL7_MASK>0x80</OCR4BL7_MASK></OCR4BL>
<OCR4AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A9</MEM_ADDR>
<OCR4AH0_MASK>0x01</OCR4AH0_MASK><OCR4AH1_MASK>0x02</OCR4AH1_MASK><OCR4AH2_MASK>0x04</OCR4AH2_MASK><OCR4AH3_MASK>0x08</OCR4AH3_MASK><OCR4AH4_MASK>0x10</OCR4AH4_MASK><OCR4AH5_MASK>0x20</OCR4AH5_MASK><OCR4AH6_MASK>0x40</OCR4AH6_MASK><OCR4AH7_MASK>0x80</OCR4AH7_MASK></OCR4AH>
<OCR4AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A8</MEM_ADDR>
<OCR4AL0_MASK>0x01</OCR4AL0_MASK><OCR4AL1_MASK>0x02</OCR4AL1_MASK><OCR4AL2_MASK>0x04</OCR4AL2_MASK><OCR4AL3_MASK>0x08</OCR4AL3_MASK><OCR4AL4_MASK>0x10</OCR4AL4_MASK><OCR4AL5_MASK>0x20</OCR4AL5_MASK><OCR4AL6_MASK>0x40</OCR4AL6_MASK><OCR4AL7_MASK>0x80</OCR4AL7_MASK></OCR4AL>
<ICR4H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A7</MEM_ADDR>
<ICR4H0_MASK>0x01</ICR4H0_MASK><ICR4H1_MASK>0x02</ICR4H1_MASK><ICR4H2_MASK>0x04</ICR4H2_MASK><ICR4H3_MASK>0x08</ICR4H3_MASK><ICR4H4_MASK>0x10</ICR4H4_MASK><ICR4H5_MASK>0x20</ICR4H5_MASK><ICR4H6_MASK>0x40</ICR4H6_MASK><ICR4H7_MASK>0x80</ICR4H7_MASK></ICR4H>
<ICR4L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A6</MEM_ADDR>
<ICR4L0_MASK>0x01</ICR4L0_MASK><ICR4L1_MASK>0x02</ICR4L1_MASK><ICR4L2_MASK>0x04</ICR4L2_MASK><ICR4L3_MASK>0x08</ICR4L3_MASK><ICR4L4_MASK>0x10</ICR4L4_MASK><ICR4L5_MASK>0x20</ICR4L5_MASK><ICR4L6_MASK>0x40</ICR4L6_MASK><ICR4L7_MASK>0x80</ICR4L7_MASK></ICR4L>
<TCNT4H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A5</MEM_ADDR>
<TCNT4H0_MASK>0x01</TCNT4H0_MASK><TCNT4H1_MASK>0x02</TCNT4H1_MASK><TCNT4H2_MASK>0x04</TCNT4H2_MASK><TCNT4H3_MASK>0x08</TCNT4H3_MASK><TCNT4H4_MASK>0x10</TCNT4H4_MASK><TCNT4H5_MASK>0x20</TCNT4H5_MASK><TCNT4H6_MASK>0x40</TCNT4H6_MASK><TCNT4H7_MASK>0x80</TCNT4H7_MASK></TCNT4H>
<TCNT4L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A4</MEM_ADDR>
<TCNT4L0_MASK>0x01</TCNT4L0_MASK><TCNT4L1_MASK>0x02</TCNT4L1_MASK><TCNT4L2_MASK>0x04</TCNT4L2_MASK><TCNT4L3_MASK>0x08</TCNT4L3_MASK><TCNT4L4_MASK>0x10</TCNT4L4_MASK><TCNT4L5_MASK>0x20</TCNT4L5_MASK><TCNT4L6_MASK>0x40</TCNT4L6_MASK><TCNT4L7_MASK>0x80</TCNT4L7_MASK></TCNT4L>
<TCCR4C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A2</MEM_ADDR>
<FOC4C_MASK>0x20</FOC4C_MASK><FOC4B_MASK>0x40</FOC4B_MASK><FOC4A_MASK>0x80</FOC4A_MASK></TCCR4C>
<TCCR4B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A1</MEM_ADDR>
<CS40_MASK>0x01</CS40_MASK><CS41_MASK>0x02</CS41_MASK><CS42_MASK>0x04</CS42_MASK><WGM42_MASK>0x08</WGM42_MASK><WGM43_MASK>0x10</WGM43_MASK><ICES4_MASK>0x40</ICES4_MASK><ICNC4_MASK>0x80</ICNC4_MASK></TCCR4B>
<TCCR4A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A0</MEM_ADDR>
<WGM40_MASK>0x01</WGM40_MASK><WGM41_MASK>0x02</WGM41_MASK><COM4C0_MASK>0x04</COM4C0_MASK><COM4C1_MASK>0x08</COM4C1_MASK><COM4B0_MASK>0x10</COM4B0_MASK><COM4B1_MASK>0x20</COM4B1_MASK><COM4A0_MASK>0x40</COM4A0_MASK><COM4A1_MASK>0x80</COM4A1_MASK></TCCR4A>
<OCR3CH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9D</MEM_ADDR>
<OCR3CH0_MASK>0x01</OCR3CH0_MASK><OCR3CH1_MASK>0x02</OCR3CH1_MASK><OCR3CH2_MASK>0x04</OCR3CH2_MASK><OCR3CH3_MASK>0x08</OCR3CH3_MASK><OCR3CH4_MASK>0x10</OCR3CH4_MASK><OCR3CH5_MASK>0x20</OCR3CH5_MASK><OCR3CH6_MASK>0x40</OCR3CH6_MASK><OCR3CH7_MASK>0x80</OCR3CH7_MASK></OCR3CH>
<OCR3CL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9C</MEM_ADDR>
<OCR3CL0_MASK>0x01</OCR3CL0_MASK><OCR3CL1_MASK>0x02</OCR3CL1_MASK><OCR3CL2_MASK>0x04</OCR3CL2_MASK><OCR3CL3_MASK>0x08</OCR3CL3_MASK><OCR3CL4_MASK>0x10</OCR3CL4_MASK><OCR3CL5_MASK>0x20</OCR3CL5_MASK><OCR3CL6_MASK>0x40</OCR3CL6_MASK><OCR3CL7_MASK>0x80</OCR3CL7_MASK></OCR3CL>
<OCR3BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9B</MEM_ADDR>
<OCR3BH0_MASK>0x01</OCR3BH0_MASK><OCR3BH1_MASK>0x02</OCR3BH1_MASK><OCR3BH2_MASK>0x04</OCR3BH2_MASK><OCR3BH3_MASK>0x08</OCR3BH3_MASK><OCR3BH4_MASK>0x10</OCR3BH4_MASK><OCR3BH5_MASK>0x20</OCR3BH5_MASK><OCR3BH6_MASK>0x40</OCR3BH6_MASK><OCR3BH7_MASK>0x80</OCR3BH7_MASK></OCR3BH>
<OCR3BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9A</MEM_ADDR>
<OCR3BL0_MASK>0x01</OCR3BL0_MASK><OCR3BL1_MASK>0x02</OCR3BL1_MASK><OCR3BL2_MASK>0x04</OCR3BL2_MASK><OCR3BL3_MASK>0x08</OCR3BL3_MASK><OCR3BL4_MASK>0x10</OCR3BL4_MASK><OCR3BL5_MASK>0x20</OCR3BL5_MASK><OCR3BL6_MASK>0x40</OCR3BL6_MASK><OCR3BL7_MASK>0x80</OCR3BL7_MASK></OCR3BL>
<OCR3AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$99</MEM_ADDR>
<OCR3AH0_MASK>0x01</OCR3AH0_MASK><OCR3AH1_MASK>0x02</OCR3AH1_MASK><OCR3AH2_MASK>0x04</OCR3AH2_MASK><OCR3AH3_MASK>0x08</OCR3AH3_MASK><OCR3AH4_MASK>0x10</OCR3AH4_MASK><OCR3AH5_MASK>0x20</OCR3AH5_MASK><OCR3AH6_MASK>0x40</OCR3AH6_MASK><OCR3AH7_MASK>0x80</OCR3AH7_MASK></OCR3AH>
<OCR3AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$98</MEM_ADDR>
<OCR3AL0_MASK>0x01</OCR3AL0_MASK><OCR3AL1_MASK>0x02</OCR3AL1_MASK><OCR3AL2_MASK>0x04</OCR3AL2_MASK><OCR3AL3_MASK>0x08</OCR3AL3_MASK><OCR3AL4_MASK>0x10</OCR3AL4_MASK><OCR3AL5_MASK>0x20</OCR3AL5_MASK><OCR3AL6_MASK>0x40</OCR3AL6_MASK><OCR3AL7_MASK>0x80</OCR3AL7_MASK></OCR3AL>
<ICR3H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$97</MEM_ADDR>
<ICR3H0_MASK>0x01</ICR3H0_MASK><ICR3H1_MASK>0x02</ICR3H1_MASK><ICR3H2_MASK>0x04</ICR3H2_MASK><ICR3H3_MASK>0x08</ICR3H3_MASK><ICR3H4_MASK>0x10</ICR3H4_MASK><ICR3H5_MASK>0x20</ICR3H5_MASK><ICR3H6_MASK>0x40</ICR3H6_MASK><ICR3H7_MASK>0x80</ICR3H7_MASK></ICR3H>
<ICR3L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$96</MEM_ADDR>
<ICR3L0_MASK>0x01</ICR3L0_MASK><ICR3L1_MASK>0x02</ICR3L1_MASK><ICR3L2_MASK>0x04</ICR3L2_MASK><ICR3L3_MASK>0x08</ICR3L3_MASK><ICR3L4_MASK>0x10</ICR3L4_MASK><ICR3L5_MASK>0x20</ICR3L5_MASK><ICR3L6_MASK>0x40</ICR3L6_MASK><ICR3L7_MASK>0x80</ICR3L7_MASK></ICR3L>
<TCNT3H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$95</MEM_ADDR>
<TCNT3H0_MASK>0x01</TCNT3H0_MASK><TCNT3H1_MASK>0x02</TCNT3H1_MASK><TCNT3H2_MASK>0x04</TCNT3H2_MASK><TCNT3H3_MASK>0x08</TCNT3H3_MASK><TCNT3H4_MASK>0x10</TCNT3H4_MASK><TCNT3H5_MASK>0x20</TCNT3H5_MASK><TCNT3H6_MASK>0x40</TCNT3H6_MASK><TCNT3H7_MASK>0x80</TCNT3H7_MASK></TCNT3H>
<TCNT3L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$94</MEM_ADDR>
<TCNT3L0_MASK>0x01</TCNT3L0_MASK><TCNT3L1_MASK>0x02</TCNT3L1_MASK><TCNT3L2_MASK>0x04</TCNT3L2_MASK><TCNT3L3_MASK>0x08</TCNT3L3_MASK><TCNT3L4_MASK>0x10</TCNT3L4_MASK><TCNT3L5_MASK>0x20</TCNT3L5_MASK><TCNT3L6_MASK>0x40</TCNT3L6_MASK><TCNT3L7_MASK>0x80</TCNT3L7_MASK></TCNT3L>
<TCCR3C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$92</MEM_ADDR>
<FOC3C_MASK>0x20</FOC3C_MASK><FOC3B_MASK>0x40</FOC3B_MASK><FOC3A_MASK>0x80</FOC3A_MASK></TCCR3C>
<TCCR3B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$91</MEM_ADDR>
<CS30_MASK>0x01</CS30_MASK><CS31_MASK>0x02</CS31_MASK><CS32_MASK>0x04</CS32_MASK><WGM32_MASK>0x08</WGM32_MASK><WGM33_MASK>0x10</WGM33_MASK><ICES3_MASK>0x40</ICES3_MASK><ICNC3_MASK>0x80</ICNC3_MASK></TCCR3B>
<TCCR3A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$90</MEM_ADDR>
<WGM30_MASK>0x01</WGM30_MASK><WGM31_MASK>0x02</WGM31_MASK><COM3C0_MASK>0x04</COM3C0_MASK><COM3C1_MASK>0x08</COM3C1_MASK><COM3B0_MASK>0x10</COM3B0_MASK><COM3B1_MASK>0x20</COM3B1_MASK><COM3A0_MASK>0x40</COM3A0_MASK><COM3A1_MASK>0x80</COM3A1_MASK></TCCR3A>
<OCR1CH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8D</MEM_ADDR>
<OCR1CH0_MASK>0x01</OCR1CH0_MASK><OCR1CH1_MASK>0x02</OCR1CH1_MASK><OCR1CH2_MASK>0x04</OCR1CH2_MASK><OCR1CH3_MASK>0x08</OCR1CH3_MASK><OCR1CH4_MASK>0x10</OCR1CH4_MASK><OCR1CH5_MASK>0x20</OCR1CH5_MASK><OCR1CH6_MASK>0x40</OCR1CH6_MASK><OCR1CH7_MASK>0x80</OCR1CH7_MASK></OCR1CH>
<OCR1CL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8C</MEM_ADDR>
<OCR1CL0_MASK>0x01</OCR1CL0_MASK><OCR1CL1_MASK>0x02</OCR1CL1_MASK><OCR1CL2_MASK>0x04</OCR1CL2_MASK><OCR1CL3_MASK>0x08</OCR1CL3_MASK><OCR1CL4_MASK>0x10</OCR1CL4_MASK><OCR1CL5_MASK>0x20</OCR1CL5_MASK><OCR1CL6_MASK>0x40</OCR1CL6_MASK><OCR1CL7_MASK>0x80</OCR1CL7_MASK></OCR1CL>
<OCR1BH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8B</MEM_ADDR>
<OCR1BH0_MASK>0x01</OCR1BH0_MASK><OCR1BH1_MASK>0x02</OCR1BH1_MASK><OCR1BH2_MASK>0x04</OCR1BH2_MASK><OCR1BH3_MASK>0x08</OCR1BH3_MASK><OCR1BH4_MASK>0x10</OCR1BH4_MASK><OCR1BH5_MASK>0x20</OCR1BH5_MASK><OCR1BH6_MASK>0x40</OCR1BH6_MASK><OCR1BH7_MASK>0x80</OCR1BH7_MASK></OCR1BH>
<OCR1BL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8A</MEM_ADDR>
<OCR1BL0_MASK>0x01</OCR1BL0_MASK><OCR1BL1_MASK>0x02</OCR1BL1_MASK><OCR1BL2_MASK>0x04</OCR1BL2_MASK><OCR1BL3_MASK>0x08</OCR1BL3_MASK><OCR1BL4_MASK>0x10</OCR1BL4_MASK><OCR1BL5_MASK>0x20</OCR1BL5_MASK><OCR1BL6_MASK>0x40</OCR1BL6_MASK><OCR1BL7_MASK>0x80</OCR1BL7_MASK></OCR1BL>
<OCR1AH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$89</MEM_ADDR>
<OCR1AH0_MASK>0x01</OCR1AH0_MASK><OCR1AH1_MASK>0x02</OCR1AH1_MASK><OCR1AH2_MASK>0x04</OCR1AH2_MASK><OCR1AH3_MASK>0x08</OCR1AH3_MASK><OCR1AH4_MASK>0x10</OCR1AH4_MASK><OCR1AH5_MASK>0x20</OCR1AH5_MASK><OCR1AH6_MASK>0x40</OCR1AH6_MASK><OCR1AH7_MASK>0x80</OCR1AH7_MASK></OCR1AH>
<OCR1AL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$88</MEM_ADDR>
<OCR1AL0_MASK>0x01</OCR1AL0_MASK><OCR1AL1_MASK>0x02</OCR1AL1_MASK><OCR1AL2_MASK>0x04</OCR1AL2_MASK><OCR1AL3_MASK>0x08</OCR1AL3_MASK><OCR1AL4_MASK>0x10</OCR1AL4_MASK><OCR1AL5_MASK>0x20</OCR1AL5_MASK><OCR1AL6_MASK>0x40</OCR1AL6_MASK><OCR1AL7_MASK>0x80</OCR1AL7_MASK></OCR1AL>
<ICR1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$87</MEM_ADDR>
<ICR1H0_MASK>0x01</ICR1H0_MASK><ICR1H1_MASK>0x02</ICR1H1_MASK><ICR1H2_MASK>0x04</ICR1H2_MASK><ICR1H3_MASK>0x08</ICR1H3_MASK><ICR1H4_MASK>0x10</ICR1H4_MASK><ICR1H5_MASK>0x20</ICR1H5_MASK><ICR1H6_MASK>0x40</ICR1H6_MASK><ICR1H7_MASK>0x80</ICR1H7_MASK></ICR1H>
<ICR1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$86</MEM_ADDR>
<ICR1L0_MASK>0x01</ICR1L0_MASK><ICR1L1_MASK>0x02</ICR1L1_MASK><ICR1L2_MASK>0x04</ICR1L2_MASK><ICR1L3_MASK>0x08</ICR1L3_MASK><ICR1L4_MASK>0x10</ICR1L4_MASK><ICR1L5_MASK>0x20</ICR1L5_MASK><ICR1L6_MASK>0x40</ICR1L6_MASK><ICR1L7_MASK>0x80</ICR1L7_MASK></ICR1L>
<TCNT1H>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$85</MEM_ADDR>
<TCNT1H0_MASK>0x01</TCNT1H0_MASK><TCNT1H1_MASK>0x02</TCNT1H1_MASK><TCNT1H2_MASK>0x04</TCNT1H2_MASK><TCNT1H3_MASK>0x08</TCNT1H3_MASK><TCNT1H4_MASK>0x10</TCNT1H4_MASK><TCNT1H5_MASK>0x20</TCNT1H5_MASK><TCNT1H6_MASK>0x40</TCNT1H6_MASK><TCNT1H7_MASK>0x80</TCNT1H7_MASK></TCNT1H>
<TCNT1L>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$84</MEM_ADDR>
<TCNT1L0_MASK>0x01</TCNT1L0_MASK><TCNT1L1_MASK>0x02</TCNT1L1_MASK><TCNT1L2_MASK>0x04</TCNT1L2_MASK><TCNT1L3_MASK>0x08</TCNT1L3_MASK><TCNT1L4_MASK>0x10</TCNT1L4_MASK><TCNT1L5_MASK>0x20</TCNT1L5_MASK><TCNT1L6_MASK>0x40</TCNT1L6_MASK><TCNT1L7_MASK>0x80</TCNT1L7_MASK></TCNT1L>
<TCCR1C>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$82</MEM_ADDR>
<FOC1C_MASK>0x20</FOC1C_MASK><FOC1B_MASK>0x40</FOC1B_MASK><FOC1A_MASK>0x80</FOC1A_MASK></TCCR1C>
<TCCR1B>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$81</MEM_ADDR>
<CS10_MASK>0x01</CS10_MASK><CS11_MASK>0x02</CS11_MASK><CS12_MASK>0x04</CS12_MASK><WGM12_MASK>0x08</WGM12_MASK><WGM13_MASK>0x10</WGM13_MASK><ICES1_MASK>0x40</ICES1_MASK><ICNC1_MASK>0x80</ICNC1_MASK></TCCR1B>
<TCCR1A>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$80</MEM_ADDR>
<WGM10_MASK>0x01</WGM10_MASK><WGM11_MASK>0x02</WGM11_MASK><COM1C0_MASK>0x04</COM1C0_MASK><COM1C1_MASK>0x08</COM1C1_MASK><COM1B0_MASK>0x10</COM1B0_MASK><COM1B1_MASK>0x20</COM1B1_MASK><COM1A0_MASK>0x40</COM1A0_MASK><COM1A1_MASK>0x80</COM1A1_MASK></TCCR1A>
<DIDR1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7F</MEM_ADDR>
<AIN0D_MASK>0x01</AIN0D_MASK><AIN1D_MASK>0x02</AIN1D_MASK></DIDR1>
<DIDR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7E</MEM_ADDR>
<ADC0D_MASK>0x01</ADC0D_MASK><ADC1D_MASK>0x02</ADC1D_MASK><ADC2D_MASK>0x04</ADC2D_MASK><ADC3D_MASK>0x08</ADC3D_MASK><ADC4D_MASK>0x10</ADC4D_MASK><ADC5D_MASK>0x20</ADC5D_MASK><ADC6D_MASK>0x40</ADC6D_MASK><ADC7D_MASK>0x80</ADC7D_MASK></DIDR0>
<DIDR2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7D</MEM_ADDR>
<ADC8D_MASK>0x01</ADC8D_MASK><ADC9D_MASK>0x02</ADC9D_MASK><ADC10D_MASK>0x04</ADC10D_MASK><ADC11D_MASK>0x08</ADC11D_MASK><ADC12D_MASK>0x10</ADC12D_MASK><ADC13D_MASK>0x20</ADC13D_MASK><ADC14D_MASK>0x40</ADC14D_MASK><ADC15D_MASK>0x80</ADC15D_MASK></DIDR2>
<ADMUX>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7C</MEM_ADDR>
<MUX0_MASK>0x01</MUX0_MASK><MUX1_MASK>0x02</MUX1_MASK><MUX2_MASK>0x04</MUX2_MASK><MUX3_MASK>0x08</MUX3_MASK><MUX4_MASK>0x10</MUX4_MASK><ADLAR_MASK>0x20</ADLAR_MASK><REFS0_MASK>0x40</REFS0_MASK><REFS1_MASK>0x80</REFS1_MASK></ADMUX>
<ADCSRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7B</MEM_ADDR>
<ACME_MASK>0x40</ACME_MASK><ADTS0_MASK>0x01</ADTS0_MASK><ADTS1_MASK>0x02</ADTS1_MASK><ADTS2_MASK>0x04</ADTS2_MASK><MUX5_MASK>0x08</MUX5_MASK></ADCSRB>
<ADCSRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7A</MEM_ADDR>
<ADPS0_MASK>0x01</ADPS0_MASK><ADPS1_MASK>0x02</ADPS1_MASK><ADPS2_MASK>0x04</ADPS2_MASK><ADIE_MASK>0x08</ADIE_MASK><ADIF_MASK>0x10</ADIF_MASK><ADATE_MASK>0x20</ADATE_MASK><ADSC_MASK>0x40</ADSC_MASK><ADEN_MASK>0x80</ADEN_MASK></ADCSRA>
<ADCH>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$79</MEM_ADDR>
<ADCH0_MASK>0x01</ADCH0_MASK><ADCH1_MASK>0x02</ADCH1_MASK><ADCH2_MASK>0x04</ADCH2_MASK><ADCH3_MASK>0x08</ADCH3_MASK><ADCH4_MASK>0x10</ADCH4_MASK><ADCH5_MASK>0x20</ADCH5_MASK><ADCH6_MASK>0x40</ADCH6_MASK><ADCH7_MASK>0x80</ADCH7_MASK></ADCH>
<ADCL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$78</MEM_ADDR>
<ADCL0_MASK>0x01</ADCL0_MASK><ADCL1_MASK>0x02</ADCL1_MASK><ADCL2_MASK>0x04</ADCL2_MASK><ADCL3_MASK>0x08</ADCL3_MASK><ADCL4_MASK>0x10</ADCL4_MASK><ADCL5_MASK>0x20</ADCL5_MASK><ADCL6_MASK>0x40</ADCL6_MASK><ADCL7_MASK>0x80</ADCL7_MASK></ADCL>
<XMCRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$75</MEM_ADDR>
<XMM0_MASK>0x01</XMM0_MASK><XMM1_MASK>0x02</XMM1_MASK><XMM2_MASK>0x04</XMM2_MASK><XMBK_MASK>0x80</XMBK_MASK></XMCRB>
<XMCRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$74</MEM_ADDR>
<SRW00_MASK>0x01</SRW00_MASK><SRW01_MASK>0x02</SRW01_MASK><SRW10_MASK>0x04</SRW10_MASK><SRW11_MASK>0x08</SRW11_MASK><SRL0_MASK>0x10</SRL0_MASK><SRL1_MASK>0x20</SRL1_MASK><SRL2_MASK>0x40</SRL2_MASK><SRE_MASK>0x80</SRE_MASK></XMCRA>
<TIMSK5>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$73</MEM_ADDR>
<TOIE5_MASK>0x01</TOIE5_MASK><OCIE5A_MASK>0x02</OCIE5A_MASK><OCIE5B_MASK>0x04</OCIE5B_MASK><OCIE5C_MASK>0x08</OCIE5C_MASK><ICIE5_MASK>0x20</ICIE5_MASK></TIMSK5>
<TIMSK4>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$72</MEM_ADDR>
<TOIE4_MASK>0x01</TOIE4_MASK><OCIE4A_MASK>0x02</OCIE4A_MASK><OCIE4B_MASK>0x04</OCIE4B_MASK><OCIE4C_MASK>0x08</OCIE4C_MASK><ICIE4_MASK>0x20</ICIE4_MASK></TIMSK4>
<TIMSK3>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$71</MEM_ADDR>
<TOIE3_MASK>0x01</TOIE3_MASK><OCIE3A_MASK>0x02</OCIE3A_MASK><OCIE3B_MASK>0x04</OCIE3B_MASK><OCIE3C_MASK>0x08</OCIE3C_MASK><ICIE3_MASK>0x20</ICIE3_MASK></TIMSK3>
<TIMSK2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$70</MEM_ADDR>
<TOIE2_MASK>0x01</TOIE2_MASK><OCIE2A_MASK>0x02</OCIE2A_MASK><OCIE2B_MASK>0x04</OCIE2B_MASK></TIMSK2>
<TIMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6F</MEM_ADDR>
<TOIE1_MASK>0x01</TOIE1_MASK><OCIE1A_MASK>0x02</OCIE1A_MASK><OCIE1B_MASK>0x04</OCIE1B_MASK><OCIE1C_MASK>0x08</OCIE1C_MASK><ICIE1_MASK>0x20</ICIE1_MASK></TIMSK1>
<TIMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6E</MEM_ADDR>
<TOIE0_MASK>0x01</TOIE0_MASK><OCIE0A_MASK>0x02</OCIE0A_MASK><OCIE0B_MASK>0x04</OCIE0B_MASK></TIMSK0>
<PCMSK2>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6D</MEM_ADDR>
<PCINT16_MASK>0x01</PCINT16_MASK><PCINT17_MASK>0x02</PCINT17_MASK><PCINT18_MASK>0x04</PCINT18_MASK><PCINT19_MASK>0x08</PCINT19_MASK><PCINT20_MASK>0x10</PCINT20_MASK><PCINT21_MASK>0x20</PCINT21_MASK><PCINT22_MASK>0x40</PCINT22_MASK><PCINT23_MASK>0x80</PCINT23_MASK></PCMSK2>
<PCMSK1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6C</MEM_ADDR>
<PCINT8_MASK>0x01</PCINT8_MASK><PCINT9_MASK>0x02</PCINT9_MASK><PCINT10_MASK>0x04</PCINT10_MASK><PCINT11_MASK>0x08</PCINT11_MASK><PCINT12_MASK>0x10</PCINT12_MASK><PCINT13_MASK>0x20</PCINT13_MASK><PCINT14_MASK>0x40</PCINT14_MASK><PCINT15_MASK>0x80</PCINT15_MASK></PCMSK1>
<PCMSK0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6B</MEM_ADDR>
<PCINT0_MASK>0x01</PCINT0_MASK><PCINT1_MASK>0x02</PCINT1_MASK><PCINT2_MASK>0x04</PCINT2_MASK><PCINT3_MASK>0x08</PCINT3_MASK><PCINT4_MASK>0x10</PCINT4_MASK><PCINT5_MASK>0x20</PCINT5_MASK><PCINT6_MASK>0x40</PCINT6_MASK><PCINT7_MASK>0x80</PCINT7_MASK></PCMSK0>
<EICRB>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6A</MEM_ADDR>
<ISC40_MASK>0x01</ISC40_MASK><ISC41_MASK>0x02</ISC41_MASK><ISC50_MASK>0x04</ISC50_MASK><ISC51_MASK>0x08</ISC51_MASK><ISC60_MASK>0x10</ISC60_MASK><ISC61_MASK>0x20</ISC61_MASK><ISC70_MASK>0x40</ISC70_MASK><ISC71_MASK>0x80</ISC71_MASK></EICRB>
<EICRA>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$69</MEM_ADDR>
<ISC00_MASK>0x01</ISC00_MASK><ISC01_MASK>0x02</ISC01_MASK><ISC10_MASK>0x04</ISC10_MASK><ISC11_MASK>0x08</ISC11_MASK><ISC20_MASK>0x10</ISC20_MASK><ISC21_MASK>0x20</ISC21_MASK><ISC30_MASK>0x40</ISC30_MASK><ISC31_MASK>0x80</ISC31_MASK></EICRA>
<PCICR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$68</MEM_ADDR>
<PCIE0_MASK>0x01</PCIE0_MASK><PCIE1_MASK>0x02</PCIE1_MASK><PCIE2_MASK>0x04</PCIE2_MASK></PCICR>
<OSCCAL>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$66</MEM_ADDR>
<CAL0_MASK>0x01</CAL0_MASK><CAL1_MASK>0x02</CAL1_MASK><CAL2_MASK>0x04</CAL2_MASK><CAL3_MASK>0x08</CAL3_MASK><CAL4_MASK>0x10</CAL4_MASK><CAL5_MASK>0x20</CAL5_MASK><CAL6_MASK>0x40</CAL6_MASK><CAL7_MASK>0x80</CAL7_MASK></OSCCAL>
<PRR1>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$65</MEM_ADDR>
<PRUSART1_MASK>0x01</PRUSART1_MASK><PRUSART2_MASK>0x02</PRUSART2_MASK><PRUSART3_MASK>0x04</PRUSART3_MASK><PRTIM3_MASK>0x08</PRTIM3_MASK><PRTIM4_MASK>0x10</PRTIM4_MASK><PRTIM5_MASK>0x20</PRTIM5_MASK></PRR1>
<PRR0>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$64</MEM_ADDR>
<PRADC_MASK>0x01</PRADC_MASK><PRUSART0_MASK>0x02</PRUSART0_MASK><PRSPI_MASK>0x04</PRSPI_MASK><PRTIM1_MASK>0x08</PRTIM1_MASK><PRTIM0_MASK>0x20</PRTIM0_MASK><PRTIM2_MASK>0x40</PRTIM2_MASK><PRTWI_MASK>0x80</PRTWI_MASK></PRR0>
<CLKPR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<CLKPS0_MASK>0x01</CLKPS0_MASK><CLKPS1_MASK>0x02</CLKPS1_MASK><CLKPS2_MASK>0x04</CLKPS2_MASK><CLKPS3_MASK>0x08</CLKPS3_MASK><CLKPCE_MASK>0x80</CLKPCE_MASK></CLKPR>
<WDTCSR>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$60</MEM_ADDR>
<WDP0_MASK>0x01</WDP0_MASK><WDP1_MASK>0x02</WDP1_MASK><WDP2_MASK>0x04</WDP2_MASK><WDE_MASK>0x08</WDE_MASK><WDCE_MASK>0x10</WDCE_MASK><WDP3_MASK>0x20</WDP3_MASK><WDIE_MASK>0x40</WDIE_MASK><WDIF_MASK>0x80</WDIF_MASK></WDTCSR>
<SREG>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<C_MASK>0x01</C_MASK><Z_MASK>0x02</Z_MASK><N_MASK>0x04</N_MASK><V_MASK>0x08</V_MASK><S_MASK>0x10</S_MASK><H_MASK>0x20</H_MASK><T_MASK>0x40</T_MASK><I_MASK>0x80</I_MASK></SREG>
<SPH>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<INIT>0x21</INIT>
<SP8_MASK>0x01</SP8_MASK><SP9_MASK>0x02</SP9_MASK><SP10_MASK>0x04</SP10_MASK><SP11_MASK>0x08</SP11_MASK><SP12_MASK>0x10</SP12_MASK><SP13_MASK>0x20</SP13_MASK><SP14_MASK>0x40</SP14_MASK><SP15_MASK>0x80</SP15_MASK></SPH>
<SPL>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<INIT>0xFF</INIT>
<SP0_MASK>0x01</SP0_MASK><SP1_MASK>0x02</SP1_MASK><SP2_MASK>0x04</SP2_MASK><SP3_MASK>0x08</SP3_MASK><SP4_MASK>0x10</SP4_MASK><SP5_MASK>0x20</SP5_MASK><SP6_MASK>0x40</SP6_MASK><SP7_MASK>0x80</SP7_MASK></SPL>
<EIND>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<EIND0_MASK>0x01</EIND0_MASK></EIND>
<RAMPZ>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<RAMPZ0_MASK>0x01</RAMPZ0_MASK><RAMPZ1_MASK>0x02</RAMPZ1_MASK></RAMPZ>
<SPMCSR>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<SPMEN_MASK>0x01</SPMEN_MASK><PGERS_MASK>0x02</PGERS_MASK><PGWRT_MASK>0x04</PGWRT_MASK><BLBSET_MASK>0x08</BLBSET_MASK><RWWSRE_MASK>0x10</RWWSRE_MASK><SIGRD_MASK>0x20</SIGRD_MASK><RWWSB_MASK>0x40</RWWSB_MASK><SPMIE_MASK>0x80</SPMIE_MASK></SPMCSR>
<MCUCR>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<JTD_MASK>0x80</JTD_MASK><IVCE_MASK>0x01</IVCE_MASK><IVSEL_MASK>0x02</IVSEL_MASK><PUD_MASK>0x10</PUD_MASK></MCUCR>
<MCUSR>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<JTRF_MASK>0x10</JTRF_MASK><PORF_MASK>0x01</PORF_MASK><EXTRF_MASK>0x02</EXTRF_MASK><BORF_MASK>0x04</BORF_MASK><WDRF_MASK>0x08</WDRF_MASK></MCUSR>
<SMCR>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<SE_MASK>0x01</SE_MASK><SM0_MASK>0x02</SM0_MASK><SM1_MASK>0x04</SM1_MASK><SM2_MASK>0x08</SM2_MASK></SMCR>
<OCDR>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<OCDR0_MASK>0x01</OCDR0_MASK><OCDR1_MASK>0x02</OCDR1_MASK><OCDR2_MASK>0x04</OCDR2_MASK><OCDR3_MASK>0x08</OCDR3_MASK><OCDR4_MASK>0x10</OCDR4_MASK><OCDR5_MASK>0x20</OCDR5_MASK><OCDR6_MASK>0x40</OCDR6_MASK><OCDR7_MASK>0x80</OCDR7_MASK></OCDR>
<ACSR>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ACIS0_MASK>0x01</ACIS0_MASK><ACIS1_MASK>0x02</ACIS1_MASK><ACIC_MASK>0x04</ACIC_MASK><ACIE_MASK>0x08</ACIE_MASK><ACI_MASK>0x10</ACI_MASK><ACO_MASK>0x20</ACO_MASK><ACBG_MASK>0x40</ACBG_MASK><ACD_MASK>0x80</ACD_MASK></ACSR>
<SPDR>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<SPDR0_MASK>0x01</SPDR0_MASK><SPDR1_MASK>0x02</SPDR1_MASK><SPDR2_MASK>0x04</SPDR2_MASK><SPDR3_MASK>0x08</SPDR3_MASK><SPDR4_MASK>0x10</SPDR4_MASK><SPDR5_MASK>0x20</SPDR5_MASK><SPDR6_MASK>0x40</SPDR6_MASK><SPDR7_MASK>0x80</SPDR7_MASK></SPDR>
<SPSR>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<SPI2X_MASK>0x01</SPI2X_MASK><WCOL_MASK>0x40</WCOL_MASK><SPIF_MASK>0x80</SPIF_MASK></SPSR>
<SPCR>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<SPR0_MASK>0x01</SPR0_MASK><SPR1_MASK>0x02</SPR1_MASK><CPHA_MASK>0x04</CPHA_MASK><CPOL_MASK>0x08</CPOL_MASK><MSTR_MASK>0x10</MSTR_MASK><DORD_MASK>0x20</DORD_MASK><SPE_MASK>0x40</SPE_MASK><SPIE_MASK>0x80</SPIE_MASK></SPCR>
<GPIOR2>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<GPIOR20_MASK>0x01</GPIOR20_MASK><GPIOR21_MASK>0x02</GPIOR21_MASK><GPIOR22_MASK>0x04</GPIOR22_MASK><GPIOR23_MASK>0x08</GPIOR23_MASK><GPIOR24_MASK>0x10</GPIOR24_MASK><GPIOR25_MASK>0x20</GPIOR25_MASK><GPIOR26_MASK>0x40</GPIOR26_MASK><GPIOR27_MASK>0x80</GPIOR27_MASK></GPIOR2>
<GPIOR1>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<GPIOR10_MASK>0x01</GPIOR10_MASK><GPIOR11_MASK>0x02</GPIOR11_MASK><GPIOR12_MASK>0x04</GPIOR12_MASK><GPIOR13_MASK>0x08</GPIOR13_MASK><GPIOR14_MASK>0x10</GPIOR14_MASK><GPIOR15_MASK>0x20</GPIOR15_MASK><GPIOR16_MASK>0x40</GPIOR16_MASK><GPIOR17_MASK>0x80</GPIOR17_MASK></GPIOR1>
<OCR0B>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<OCR0B_0_MASK>0x01</OCR0B_0_MASK><OCR0B_1_MASK>0x02</OCR0B_1_MASK><OCR0B_2_MASK>0x04</OCR0B_2_MASK><OCR0B_3_MASK>0x08</OCR0B_3_MASK><OCR0B_4_MASK>0x10</OCR0B_4_MASK><OCR0B_5_MASK>0x20</OCR0B_5_MASK><OCR0B_6_MASK>0x40</OCR0B_6_MASK><OCR0B_7_MASK>0x80</OCR0B_7_MASK></OCR0B>
<OCR0A>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<OCROA_0_MASK>0x01</OCROA_0_MASK><OCROA_1_MASK>0x02</OCROA_1_MASK><OCROA_2_MASK>0x04</OCROA_2_MASK><OCROA_3_MASK>0x08</OCROA_3_MASK><OCROA_4_MASK>0x10</OCROA_4_MASK><OCROA_5_MASK>0x20</OCROA_5_MASK><OCROA_6_MASK>0x40</OCROA_6_MASK><OCROA_7_MASK>0x80</OCROA_7_MASK></OCR0A>
<TCNT0>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<TCNT0_0_MASK>0x01</TCNT0_0_MASK><TCNT0_1_MASK>0x02</TCNT0_1_MASK><TCNT0_2_MASK>0x04</TCNT0_2_MASK><TCNT0_3_MASK>0x08</TCNT0_3_MASK><TCNT0_4_MASK>0x10</TCNT0_4_MASK><TCNT0_5_MASK>0x20</TCNT0_5_MASK><TCNT0_6_MASK>0x40</TCNT0_6_MASK><TCNT0_7_MASK>0x80</TCNT0_7_MASK></TCNT0>
<TCCR0B>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<CS00_MASK>0x01</CS00_MASK><CS01_MASK>0x02</CS01_MASK><CS02_MASK>0x04</CS02_MASK><WGM02_MASK>0x08</WGM02_MASK><FOC0B_MASK>0x40</FOC0B_MASK><FOC0A_MASK>0x80</FOC0A_MASK></TCCR0B>
<TCCR0A>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<WGM00_MASK>0x01</WGM00_MASK><WGM01_MASK>0x02</WGM01_MASK><COM0B0_MASK>0x10</COM0B0_MASK><COM0B1_MASK>0x20</COM0B1_MASK><COM0A0_MASK>0x40</COM0A0_MASK><COM0A1_MASK>0x80</COM0A1_MASK></TCCR0A>
<GTCCR>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<PSRSYNC_MASK>0x01</PSRSYNC_MASK><TSM_MASK>0x80</TSM_MASK><PSRASY_MASK>0x02</PSRASY_MASK></GTCCR>
<EEARH>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<EEAR8_MASK>0x01</EEAR8_MASK><EEAR9_MASK>0x02</EEAR9_MASK><EEAR10_MASK>0x04</EEAR10_MASK><EEAR11_MASK>0x08</EEAR11_MASK></EEARH>
<EEARL>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<EEAR0_MASK>0x01</EEAR0_MASK><EEAR1_MASK>0x02</EEAR1_MASK><EEAR2_MASK>0x04</EEAR2_MASK><EEAR3_MASK>0x08</EEAR3_MASK><EEAR4_MASK>0x10</EEAR4_MASK><EEAR5_MASK>0x20</EEAR5_MASK><EEAR6_MASK>0x40</EEAR6_MASK><EEAR7_MASK>0x80</EEAR7_MASK></EEARL>
<EEDR>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<EEDR0_MASK>0x01</EEDR0_MASK><EEDR1_MASK>0x02</EEDR1_MASK><EEDR2_MASK>0x04</EEDR2_MASK><EEDR3_MASK>0x08</EEDR3_MASK><EEDR4_MASK>0x10</EEDR4_MASK><EEDR5_MASK>0x20</EEDR5_MASK><EEDR6_MASK>0x40</EEDR6_MASK><EEDR7_MASK>0x80</EEDR7_MASK></EEDR>
<EECR>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<EERE_MASK>0x01</EERE_MASK><EEPE_MASK>0x02</EEPE_MASK><EEMPE_MASK>0x04</EEMPE_MASK><EERIE_MASK>0x08</EERIE_MASK><EEPM0_MASK>0x10</EEPM0_MASK><EEPM1_MASK>0x20</EEPM1_MASK></EECR>
<GPIOR0>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<GPIOR00_MASK>0x01</GPIOR00_MASK><GPIOR01_MASK>0x02</GPIOR01_MASK><GPIOR02_MASK>0x04</GPIOR02_MASK><GPIOR03_MASK>0x08</GPIOR03_MASK><GPIOR04_MASK>0x10</GPIOR04_MASK><GPIOR05_MASK>0x20</GPIOR05_MASK><GPIOR06_MASK>0x40</GPIOR06_MASK><GPIOR07_MASK>0x80</GPIOR07_MASK></GPIOR0>
<EIMSK>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<INT0_MASK>0x01</INT0_MASK><INT1_MASK>0x02</INT1_MASK><INT2_MASK>0x04</INT2_MASK><INT3_MASK>0x08</INT3_MASK><INT4_MASK>0x10</INT4_MASK><INT5_MASK>0x20</INT5_MASK><INT6_MASK>0x40</INT6_MASK><INT7_MASK>0x80</INT7_MASK></EIMSK>
<EIFR>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<INTF0_MASK>0x01</INTF0_MASK><INTF1_MASK>0x02</INTF1_MASK><INTF2_MASK>0x04</INTF2_MASK><INTF3_MASK>0x08</INTF3_MASK><INTF4_MASK>0x10</INTF4_MASK><INTF5_MASK>0x20</INTF5_MASK><INTF6_MASK>0x40</INTF6_MASK><INTF7_MASK>0x80</INTF7_MASK></EIFR>
<PCIFR>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<PCIF0_MASK>0x01</PCIF0_MASK><PCIF1_MASK>0x02</PCIF1_MASK><PCIF2_MASK>0x04</PCIF2_MASK></PCIFR>
<TIFR5>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<TOV5_MASK>0x01</TOV5_MASK><OCF5A_MASK>0x02</OCF5A_MASK><OCF5B_MASK>0x04</OCF5B_MASK><OCF5C_MASK>0x08</OCF5C_MASK><ICF5_MASK>0x20</ICF5_MASK></TIFR5>
<TIFR4>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<TOV4_MASK>0x01</TOV4_MASK><OCF4A_MASK>0x02</OCF4A_MASK><OCF4B_MASK>0x04</OCF4B_MASK><OCF4C_MASK>0x08</OCF4C_MASK><ICF4_MASK>0x20</ICF4_MASK></TIFR4>
<TIFR3>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<TOV3_MASK>0x01</TOV3_MASK><OCF3A_MASK>0x02</OCF3A_MASK><OCF3B_MASK>0x04</OCF3B_MASK><OCF3C_MASK>0x08</OCF3C_MASK><ICF3_MASK>0x20</ICF3_MASK></TIFR3>
<TIFR2>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<TOV2_MASK>0x01</TOV2_MASK><OCF2A_MASK>0x02</OCF2A_MASK><OCF2B_MASK>0x04</OCF2B_MASK></TIFR2>
<TIFR1>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<TOV1_MASK>0x01</TOV1_MASK><OCF1A_MASK>0x02</OCF1A_MASK><OCF1B_MASK>0x04</OCF1B_MASK><OCF1C_MASK>0x08</OCF1C_MASK><ICF1_MASK>0x20</ICF1_MASK></TIFR1>
<TIFR0>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<TOV0_MASK>0x01</TOV0_MASK><OCF0A_MASK>0x02</OCF0A_MASK><OCF0B_MASK>0x04</OCF0B_MASK></TIFR0>
<PORTG>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<PORTG0_MASK>0x01</PORTG0_MASK><PORTG1_MASK>0x02</PORTG1_MASK><PORTG2_MASK>0x04</PORTG2_MASK><PORTG3_MASK>0x08</PORTG3_MASK><PORTG4_MASK>0x10</PORTG4_MASK><PORTG5_MASK>0x20</PORTG5_MASK></PORTG>
<DDRG>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<DDG0_MASK>0x01</DDG0_MASK><DDG1_MASK>0x02</DDG1_MASK><DDG2_MASK>0x04</DDG2_MASK><DDG3_MASK>0x08</DDG3_MASK><DDG4_MASK>0x10</DDG4_MASK><DDG5_MASK>0x20</DDG5_MASK></DDRG>
<PING>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<PING0_MASK>0x01</PING0_MASK><PING1_MASK>0x02</PING1_MASK><PING2_MASK>0x04</PING2_MASK><PING3_MASK>0x08</PING3_MASK><PING4_MASK>0x10</PING4_MASK><PING5_MASK>0x20</PING5_MASK></PING>
<PORTF>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<PORTF0_MASK>0x01</PORTF0_MASK><PORTF1_MASK>0x02</PORTF1_MASK><PORTF2_MASK>0x04</PORTF2_MASK><PORTF3_MASK>0x08</PORTF3_MASK><PORTF4_MASK>0x10</PORTF4_MASK><PORTF5_MASK>0x20</PORTF5_MASK><PORTF6_MASK>0x40</PORTF6_MASK><PORTF7_MASK>0x80</PORTF7_MASK></PORTF>
<DDRF>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<DDF0_MASK>0x01</DDF0_MASK><DDF1_MASK>0x02</DDF1_MASK><DDF2_MASK>0x04</DDF2_MASK><DDF3_MASK>0x08</DDF3_MASK><DDF4_MASK>0x10</DDF4_MASK><DDF5_MASK>0x20</DDF5_MASK><DDF6_MASK>0x40</DDF6_MASK><DDF7_MASK>0x80</DDF7_MASK></DDRF>
<PINF>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<PINF0_MASK>0x01</PINF0_MASK><PINF1_MASK>0x02</PINF1_MASK><PINF2_MASK>0x04</PINF2_MASK><PINF3_MASK>0x08</PINF3_MASK><PINF4_MASK>0x10</PINF4_MASK><PINF5_MASK>0x20</PINF5_MASK><PINF6_MASK>0x40</PINF6_MASK><PINF7_MASK>0x80</PINF7_MASK></PINF>
<PORTE>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<PORTE0_MASK>0x01</PORTE0_MASK><PORTE1_MASK>0x02</PORTE1_MASK><PORTE2_MASK>0x04</PORTE2_MASK><PORTE3_MASK>0x08</PORTE3_MASK><PORTE4_MASK>0x10</PORTE4_MASK><PORTE5_MASK>0x20</PORTE5_MASK><PORTE6_MASK>0x40</PORTE6_MASK><PORTE7_MASK>0x80</PORTE7_MASK></PORTE>
<DDRE>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<DDE0_MASK>0x01</DDE0_MASK><DDE1_MASK>0x02</DDE1_MASK><DDE2_MASK>0x04</DDE2_MASK><DDE3_MASK>0x08</DDE3_MASK><DDE4_MASK>0x10</DDE4_MASK><DDE5_MASK>0x20</DDE5_MASK><DDE6_MASK>0x40</DDE6_MASK><DDE7_MASK>0x80</DDE7_MASK></DDRE>
<PINE>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<PINE0_MASK>0x01</PINE0_MASK><PINE1_MASK>0x02</PINE1_MASK><PINE2_MASK>0x04</PINE2_MASK><PINE3_MASK>0x08</PINE3_MASK><PINE4_MASK>0x10</PINE4_MASK><PINE5_MASK>0x20</PINE5_MASK><PINE6_MASK>0x40</PINE6_MASK><PINE7_MASK>0x80</PINE7_MASK></PINE>
<PORTD>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<PORTD0_MASK>0x01</PORTD0_MASK><PORTD1_MASK>0x02</PORTD1_MASK><PORTD2_MASK>0x04</PORTD2_MASK><PORTD3_MASK>0x08</PORTD3_MASK><PORTD4_MASK>0x10</PORTD4_MASK><PORTD5_MASK>0x20</PORTD5_MASK><PORTD6_MASK>0x40</PORTD6_MASK><PORTD7_MASK>0x80</PORTD7_MASK></PORTD>
<DDRD>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<DDD0_MASK>0x01</DDD0_MASK><DDD1_MASK>0x02</DDD1_MASK><DDD2_MASK>0x04</DDD2_MASK><DDD3_MASK>0x08</DDD3_MASK><DDD4_MASK>0x10</DDD4_MASK><DDD5_MASK>0x20</DDD5_MASK><DDD6_MASK>0x40</DDD6_MASK><DDD7_MASK>0x80</DDD7_MASK></DDRD>
<PIND>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<PIND0_MASK>0x01</PIND0_MASK><PIND1_MASK>0x02</PIND1_MASK><PIND2_MASK>0x04</PIND2_MASK><PIND3_MASK>0x08</PIND3_MASK><PIND4_MASK>0x10</PIND4_MASK><PIND5_MASK>0x20</PIND5_MASK><PIND6_MASK>0x40</PIND6_MASK><PIND7_MASK>0x80</PIND7_MASK></PIND>
<PORTC>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<PORTC0_MASK>0x01</PORTC0_MASK><PORTC1_MASK>0x02</PORTC1_MASK><PORTC2_MASK>0x04</PORTC2_MASK><PORTC3_MASK>0x08</PORTC3_MASK><PORTC4_MASK>0x10</PORTC4_MASK><PORTC5_MASK>0x20</PORTC5_MASK><PORTC6_MASK>0x40</PORTC6_MASK><PORTC7_MASK>0x80</PORTC7_MASK></PORTC>
<DDRC>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<DDC0_MASK>0x01</DDC0_MASK><DDC1_MASK>0x02</DDC1_MASK><DDC2_MASK>0x04</DDC2_MASK><DDC3_MASK>0x08</DDC3_MASK><DDC4_MASK>0x10</DDC4_MASK><DDC5_MASK>0x20</DDC5_MASK><DDC6_MASK>0x40</DDC6_MASK><DDC7_MASK>0x80</DDC7_MASK></DDRC>
<PINC>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<PINC0_MASK>0x01</PINC0_MASK><PINC1_MASK>0x02</PINC1_MASK><PINC2_MASK>0x04</PINC2_MASK><PINC3_MASK>0x08</PINC3_MASK><PINC4_MASK>0x10</PINC4_MASK><PINC5_MASK>0x20</PINC5_MASK><PINC6_MASK>0x40</PINC6_MASK><PINC7_MASK>0x80</PINC7_MASK></PINC>
<PORTB>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<PORTB0_MASK>0x01</PORTB0_MASK><PORTB1_MASK>0x02</PORTB1_MASK><PORTB2_MASK>0x04</PORTB2_MASK><PORTB3_MASK>0x08</PORTB3_MASK><PORTB4_MASK>0x10</PORTB4_MASK><PORTB5_MASK>0x20</PORTB5_MASK><PORTB6_MASK>0x40</PORTB6_MASK><PORTB7_MASK>0x80</PORTB7_MASK></PORTB>
<DDRB>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<DDB0_MASK>0x01</DDB0_MASK><DDB1_MASK>0x02</DDB1_MASK><DDB2_MASK>0x04</DDB2_MASK><DDB3_MASK>0x08</DDB3_MASK><DDB4_MASK>0x10</DDB4_MASK><DDB5_MASK>0x20</DDB5_MASK><DDB6_MASK>0x40</DDB6_MASK><DDB7_MASK>0x80</DDB7_MASK></DDRB>
<PINB>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<PINB0_MASK>0x01</PINB0_MASK><PINB1_MASK>0x02</PINB1_MASK><PINB2_MASK>0x04</PINB2_MASK><PINB3_MASK>0x08</PINB3_MASK><PINB4_MASK>0x10</PINB4_MASK><PINB5_MASK>0x20</PINB5_MASK><PINB6_MASK>0x40</PINB6_MASK><PINB7_MASK>0x80</PINB7_MASK></PINB>
<PORTA>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<PORTA0_MASK>0x01</PORTA0_MASK><PORTA1_MASK>0x02</PORTA1_MASK><PORTA2_MASK>0x04</PORTA2_MASK><PORTA3_MASK>0x08</PORTA3_MASK><PORTA4_MASK>0x10</PORTA4_MASK><PORTA5_MASK>0x20</PORTA5_MASK><PORTA6_MASK>0x40</PORTA6_MASK><PORTA7_MASK>0x80</PORTA7_MASK></PORTA>
<DDRA>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<DDA0_MASK>0x01</DDA0_MASK><DDA1_MASK>0x02</DDA1_MASK><DDA2_MASK>0x04</DDA2_MASK><DDA3_MASK>0x08</DDA3_MASK><DDA4_MASK>0x10</DDA4_MASK><DDA5_MASK>0x20</DDA5_MASK><DDA6_MASK>0x40</DDA6_MASK><DDA7_MASK>0x80</DDA7_MASK></DDRA>
<PINA>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<PINA0_MASK>0x01</PINA0_MASK><PINA1_MASK>0x02</PINA1_MASK><PINA2_MASK>0x04</PINA2_MASK><PINA3_MASK>0x08</PINA3_MASK><PINA4_MASK>0x10</PINA4_MASK><PINA5_MASK>0x20</PINA5_MASK><PINA6_MASK>0x40</PINA6_MASK><PINA7_MASK>0x80</PINA7_MASK></PINA>
</IO_MEMORY>
<BOOT_CONFIG>
<NRWW_START_ADDR>$7000</NRWW_START_ADDR>
<NRWW_STOP_ADDR>$7FFF</NRWW_STOP_ADDR>
<RWW_START_ADDR>$0000</RWW_START_ADDR>
<RWW_STOP_ADDR>$6FFF</RWW_STOP_ADDR>
<PAGESIZE>128</PAGESIZE>
<BOOTSZMODE1>
<BOOTSIZE>512</BOOTSIZE>
<PAGES>4</PAGES>
<APPSTART>$0000</APPSTART>
<BOOTSTART>$7E00</BOOTSTART>
<BOOTRESET>$7E00</BOOTRESET>
</BOOTSZMODE1>
<BOOTSZMODE2>
<BOOTSIZE>1024</BOOTSIZE>
<PAGES>8</PAGES>
<APPSTART>$0000</APPSTART>
<BOOTSTART>$7C00</BOOTSTART>
<BOOTRESET>$7C00</BOOTRESET>
</BOOTSZMODE2>
<BOOTSZMODE3>
<BOOTSIZE>2048</BOOTSIZE>
<PAGES>16</PAGES>
<APPSTART>$0000</APPSTART>
<BOOTSTART>$7800</BOOTSTART>
<BOOTRESET>$7800</BOOTRESET>
</BOOTSZMODE3>
<BOOTSZMODE4>
<BOOTSIZE>4096</BOOTSIZE>
<PAGES>32</PAGES>
<APPSTART>$0000</APPSTART>
<BOOTSTART>$7000</BOOTSTART>
<BOOTRESET>$7000</BOOTRESET>
</BOOTSZMODE4>
</BOOT_CONFIG>
</MEMORY>
<FUSE>
<LIST>[LOW:HIGH:EXTENDED]</LIST>
<ID/>
<ICON/>
<TEXT/>
<LOW>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>CLKDIV8</NAME>
<TEXT>Divide clock by 8</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>CKOUT</NAME>
<TEXT>Clock output</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SUT1</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>SUT0</NAME>
<TEXT>Select start-up time</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>CKSEL3</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>CKSEL2</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>CKSEL1</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>CKSEL0</NAME>
<TEXT>Select Clock Source</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE0>
<NMB_TEXT>57</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>Divide clock by 8 internally; [CKDIV8=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>Clock output on PORTE7; [CKOUT=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x3F</MASK>
<VALUE>0x00</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x3F</MASK>
<VALUE>0x10</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 4.1 ms; [CKSEL=0000 SUT=01]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x3F</MASK>
<VALUE>0x20</VALUE>
<TEXT>Ext. Clock; Start-up time: 6 CK + 65 ms; [CKSEL=0000 SUT=10]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x3F</MASK>
<VALUE>0x02</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x3F</MASK>
<VALUE>0x12</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 4.1 ms; [CKSEL=0010 SUT=01]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x3F</MASK>
<VALUE>0x22</VALUE>
<TEXT>Int. RC Osc.; Start-up time: 6 CK + 65 ms; [CKSEL=0010 SUT=10]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x3F</MASK>
<VALUE>0x03</VALUE>
<TEXT>Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00]</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x3F</MASK>
<VALUE>0x13</VALUE>
<TEXT>Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01]</TEXT>
</TEXT10>
<TEXT11>
<MASK>0x3F</MASK>
<VALUE>0x23</VALUE>
<TEXT>Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10]</TEXT>
</TEXT11>
<TEXT12>
<MASK>0x3F</MASK>
<VALUE>0x04</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; [CKSEL=0100 SUT=00]</TEXT>
</TEXT12>
<TEXT13>
<MASK>0x3F</MASK>
<VALUE>0x14</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; [CKSEL=0100 SUT=01]</TEXT>
</TEXT13>
<TEXT14>
<MASK>0x3F</MASK>
<VALUE>0x24</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; [CKSEL=0100 SUT=10]</TEXT>
</TEXT14>
<TEXT15>
<MASK>0x3F</MASK>
<VALUE>0x05</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; [CKSEL=0101 SUT=00]</TEXT>
</TEXT15>
<TEXT16>
<MASK>0x3F</MASK>
<VALUE>0x15</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; [CKSEL=0101 SUT=01]</TEXT>
</TEXT16>
<TEXT17>
<MASK>0x3F</MASK>
<VALUE>0x25</VALUE>
<TEXT>Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; [CKSEL=0101 SUT=10]</TEXT>
</TEXT17>
<TEXT18>
<MASK>0x3F</MASK>
<VALUE>0x06</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=00]</TEXT>
</TEXT18>
<TEXT19>
<MASK>0x3F</MASK>
<VALUE>0x16</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0110 SUT=01]</TEXT>
</TEXT19>
<TEXT20>
<MASK>0x3F</MASK>
<VALUE>0x26</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable; [CKSEL=0110 SUT=10]</TEXT>
</TEXT20>
<TEXT21>
<MASK>0x3F</MASK>
<VALUE>0x36</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=11]</TEXT>
</TEXT21>
<TEXT22>
<MASK>0x3F</MASK>
<VALUE>0x07</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0111 SUT=00]</TEXT>
</TEXT22>
<TEXT23>
<MASK>0x3F</MASK>
<VALUE>0x17</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled; [CKSEL=0111 SUT=01]</TEXT>
</TEXT23>
<TEXT24>
<MASK>0x3F</MASK>
<VALUE>0x27</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power; [CKSEL=0111 SUT=10]</TEXT>
</TEXT24>
<TEXT25>
<MASK>0x3F</MASK>
<VALUE>0x37</VALUE>
<TEXT>Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power; [CKSEL=0111 SUT=11]</TEXT>
</TEXT25>
<TEXT26>
<MASK>0x3F</MASK>
<VALUE>0x08</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1000 SUT=00]</TEXT>
</TEXT26>
<TEXT27>
<MASK>0x3F</MASK>
<VALUE>0x18</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1000 SUT=01]</TEXT>
</TEXT27>
<TEXT28>
<MASK>0x3F</MASK>
<VALUE>0x28</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1000 SUT=10]</TEXT>
</TEXT28>
<TEXT29>
<MASK>0x3F</MASK>
<VALUE>0x38</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1000 SUT=11]</TEXT>
</TEXT29>
<TEXT30>
<MASK>0x3F</MASK>
<VALUE>0x09</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1001 SUT=00]</TEXT>
</TEXT30>
<TEXT31>
<MASK>0x3F</MASK>
<VALUE>0x19</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1001 SUT=01]</TEXT>
</TEXT31>
<TEXT32>
<MASK>0x3F</MASK>
<VALUE>0x29</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1001 SUT=10]</TEXT>
</TEXT32>
<TEXT33>
<MASK>0x3F</MASK>
<VALUE>0x39</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1001 SUT=11]</TEXT>
</TEXT33>
<TEXT34>
<MASK>0x3F</MASK>
<VALUE>0x0A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1010 SUT=00]</TEXT>
</TEXT34>
<TEXT35>
<MASK>0x3F</MASK>
<VALUE>0x1A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1010 SUT=01]</TEXT>
</TEXT35>
<TEXT36>
<MASK>0x3F</MASK>
<VALUE>0x2A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]</TEXT>
</TEXT36>
<TEXT37>
<MASK>0x3F</MASK>
<VALUE>0x3A</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1010 SUT=11]</TEXT>
</TEXT37>
<TEXT38>
<MASK>0x3F</MASK>
<VALUE>0x0B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1011 SUT=00]</TEXT>
</TEXT38>
<TEXT39>
<MASK>0x3F</MASK>
<VALUE>0x1B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]</TEXT>
</TEXT39>
<TEXT40>
<MASK>0x3F</MASK>
<VALUE>0x2B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1011 SUT=10]</TEXT>
</TEXT40>
<TEXT41>
<MASK>0x3F</MASK>
<VALUE>0x3B</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1011 SUT=11]</TEXT>
</TEXT41>
<TEXT42>
<MASK>0x3F</MASK>
<VALUE>0x0C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1100 SUT=00]</TEXT>
</TEXT42>
<TEXT43>
<MASK>0x3F</MASK>
<VALUE>0x1C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1100 SUT=01]</TEXT>
</TEXT43>
<TEXT44>
<MASK>0x3F</MASK>
<VALUE>0x2C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]</TEXT>
</TEXT44>
<TEXT45>
<MASK>0x3F</MASK>
<VALUE>0x3C</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1100 SUT=11]</TEXT>
</TEXT45>
<TEXT46>
<MASK>0x3F</MASK>
<VALUE>0x0D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1101 SUT=00]</TEXT>
</TEXT46>
<TEXT47>
<MASK>0x3F</MASK>
<VALUE>0x1D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]</TEXT>
</TEXT47>
<TEXT48>
<MASK>0x3F</MASK>
<VALUE>0x2D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1101 SUT=10]</TEXT>
</TEXT48>
<TEXT49>
<MASK>0x3F</MASK>
<VALUE>0x3D</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1101 SUT=11]</TEXT>
</TEXT49>
<TEXT50>
<MASK>0x3F</MASK>
<VALUE>0x0E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1110 SUT=00]</TEXT>
</TEXT50>
<TEXT51>
<MASK>0x3F</MASK>
<VALUE>0x1E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1110 SUT=01]</TEXT>
</TEXT51>
<TEXT52>
<MASK>0x3F</MASK>
<VALUE>0x2E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]</TEXT>
</TEXT52>
<TEXT53>
<MASK>0x3F</MASK>
<VALUE>0x3E</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1110 SUT=11]</TEXT>
</TEXT53>
<TEXT54>
<MASK>0x3F</MASK>
<VALUE>0x0F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1111 SUT=00]</TEXT>
</TEXT54>
<TEXT55>
<MASK>0x3F</MASK>
<VALUE>0x1F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]</TEXT>
</TEXT55>
<TEXT56>
<MASK>0x3F</MASK>
<VALUE>0x2F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1111 SUT=10]</TEXT>
</TEXT56>
<TEXT57>
<MASK>0x3F</MASK>
<VALUE>0x3F</VALUE>
<TEXT>Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1111 SUT=11]</TEXT>
</TEXT57>
</LOW>
<HIGH>
<NMB_FUSE_BITS>8</NMB_FUSE_BITS>
<FUSE7>
<NAME>OCDEN</NAME>
<TEXT>Enable OCD</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE7>
<FUSE6>
<NAME>JTAGEN</NAME>
<TEXT>Enable JTAG</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE6>
<FUSE5>
<NAME>SPIEN</NAME>
<TEXT>Enable Serial programming and Data Downloading</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE5>
<FUSE4>
<NAME>WDTON</NAME>
<TEXT>Watchdog timer always on</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE4>
<FUSE3>
<NAME>EESAVE</NAME>
<TEXT>EEPROM memory is preserved through chip erase</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE3>
<FUSE2>
<NAME>BOOTSZ1</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BOOTSZ0</NAME>
<TEXT>Select Boot Size</TEXT>
<DEFAULT>0</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>BOOTRST</NAME>
<TEXT>Select Reset Vector</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>10</NMB_TEXT>
<TEXT1>
<MASK>0x80</MASK>
<VALUE>0x00</VALUE>
<TEXT>On-Chip Debug Enabled; [OCDEN=0]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x40</MASK>
<VALUE>0x00</VALUE>
<TEXT>JTAG Interface Enabled; [JTAGEN=0]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x20</MASK>
<VALUE>0x00</VALUE>
<TEXT>Serial program downloading (SPI) enabled; [SPIEN=0]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x10</MASK>
<VALUE>0x00</VALUE>
<TEXT>Watchdog timer always on; [WDTON=0]</TEXT>
</TEXT4>
<TEXT5>
<MASK>0x08</MASK>
<VALUE>0x00</VALUE>
<TEXT>Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]</TEXT>
</TEXT5>
<TEXT6>
<MASK>0x06</MASK>
<VALUE>0x06</VALUE>
<TEXT>Boot Flash section size=512 words Boot start address=$7E00; [BOOTSZ=11]</TEXT>
</TEXT6>
<TEXT7>
<MASK>0x06</MASK>
<VALUE>0x04</VALUE>
<TEXT>Boot Flash section size=1024 words Boot start address=$7C00; [BOOTSZ=10]</TEXT>
</TEXT7>
<TEXT8>
<MASK>0x06</MASK>
<VALUE>0x02</VALUE>
<TEXT>Boot Flash section size=2048 words Boot start address=$7800; [BOOTSZ=01]</TEXT>
</TEXT8>
<TEXT9>
<MASK>0x06</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Flash section size=4096 words Boot start address=$7000; [BOOTSZ=00] ; default value</TEXT>
</TEXT9>
<TEXT10>
<MASK>0x01</MASK>
<VALUE>0x00</VALUE>
<TEXT>Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]</TEXT>
</TEXT10>
</HIGH>
<EXTENDED>
<NMB_FUSE_BITS>3</NMB_FUSE_BITS>
<FUSE2>
<NAME>BODLEVEL2</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE2>
<FUSE1>
<NAME>BODLEVEL1</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE1>
<FUSE0>
<NAME>BODLEVEL0</NAME>
<TEXT>Brown-out Detector trigger level</TEXT>
<DEFAULT>1</DEFAULT>
</FUSE0>
<NMB_TEXT>4</NMB_TEXT>
<TEXT1>
<MASK>0x07</MASK>
<VALUE>0x07</VALUE>
<TEXT>Brown-out detection disabled; [BODLEVEL=111]</TEXT>
</TEXT1>
<TEXT2>
<MASK>0x07</MASK>
<VALUE>0x06</VALUE>
<TEXT>Brown-out detection level at VCC=1.8 V; [BODLEVEL=110]</TEXT>
</TEXT2>
<TEXT3>
<MASK>0x07</MASK>
<VALUE>0x05</VALUE>
<TEXT>Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]</TEXT>
</TEXT3>
<TEXT4>
<MASK>0x07</MASK>
<VALUE>0x04</VALUE>
<TEXT>Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]</TEXT>
</TEXT4>
</EXTENDED>
</FUSE>
<IO_MODULE><MODULE_LIST>[ANALOG_COMPARATOR:USART0:TWI:SPI:PORTA:PORTB:PORTC:PORTD:PORTE:PORTF:PORTG:PORTH:PORTJ:PORTK:PORTL:TIMER_COUNTER_0:TIMER_COUNTER_2:WATCHDOG:USART1:EEPROM:TIMER_COUNTER_5:TIMER_COUNTER_4:TIMER_COUNTER_3:TIMER_COUNTER_1:JTAG:EXTERNAL_INTERRUPT:CPU:AD_CONVERTER:BOOT_LOAD:USART2:USART3]</MODULE_LIST><ANALOG_COMPARATOR>
<LIST>[ADCSRB:ACSR:DIDR1]</LIST>
<LINK/>
<ICON>io_analo.bmp</ICON>
<ID>AlgComp_01</ID>
<TEXT/>
<ADCSRB>
<NAME>ADCSRB</NAME>
<DESCRIPTION>ADC Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>ACME</NAME>
<DESCRIPTION>Analog Comparator Multiplexer Enable</DESCRIPTION>
<TEXT>When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
</ADCSRB>
<ACSR>
<NAME>ACSR</NAME>
<DESCRIPTION>Analog Comparator Control And Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$30</IO_ADDR>
<MEM_ADDR>$50</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ACD</NAME>
<DESCRIPTION>Analog Comparator Disable</DESCRIPTION>
<TEXT>When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ACBG</NAME>
<DESCRIPTION>Analog Comparator Bandgap Select</DESCRIPTION>
<TEXT>When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ACO</NAME>
<DESCRIPTION>Analog Compare Output</DESCRIPTION>
<TEXT>The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>NA</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ACI</NAME>
<DESCRIPTION>Analog Comparator Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ACIE</NAME>
<DESCRIPTION>Analog Comparator Interrupt Enable</DESCRIPTION>
<TEXT>When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ACIC</NAME>
<DESCRIPTION>Analog Comparator Input Capture Enable</DESCRIPTION>
<TEXT>When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ACIS1</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 1</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ACIS0</NAME>
<DESCRIPTION>Analog Comparator Interrupt Mode Select bit 0</DESCRIPTION>
<TEXT>These bits determine which comparator events that trigger the Analog Comparator interrupt.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ACSR>
<DIDR1>
<NAME>DIDR1</NAME>
<DESCRIPTION>Digital Input Disable Register 1</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7F</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT1>
<NAME>AIN1D</NAME>
<DESCRIPTION>AIN1 Digital Input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>AIN0D</NAME>
<DESCRIPTION>AIN0 Digital Input Disable</DESCRIPTION>
<TEXT>When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DIDR1>
</ANALOG_COMPARATOR>
<USART0>
<LIST>[UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L]</LIST>
<LINK>[UBRR0H:UBRR0L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica</TEXT>
<UDR0>
<NAME>UDR0</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C6</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR0-7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR0-6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR0-5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR0-4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR0-3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR0-2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR0-1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR0-0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR0>
<UCSR0A>
<NAME>UCSR0A</NAME>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C0</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC0</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC0</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE0</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE0</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR0</NAME>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE0</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X0</NAME>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM0</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0A>
<UCSR0B>
<NAME>UCSR0B</NAME>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C1</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE0</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE0</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE0</NAME>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN0</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN0</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ02</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB80</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB80</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0B>
<UCSR0C>
<NAME>UCSR0C</NAME>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C2</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UMSEL01</NAME>
<ALIAS>UMSEL1</ALIAS>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL00</NAME>
<ALIAS>UMSEL0</ALIAS>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM01</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM00</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS0</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ01</NAME>
<ALIAS>UDORD0</ALIAS>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ00</NAME>
<ALIAS>UCPHA0</ALIAS>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL0</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR0C>
<UBRR0H>
<NAME>UBRR0H</NAME>
<DESCRIPTION>USART Baud Rate Register High Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C5</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR0H>
<UBRR0L>
<NAME>UBRR0L</NAME>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C4</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR0L>
</USART0>
<TWI>
<LIST>[TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr</TEXT>
<TWAMR>
<NAME>TWAMR</NAME>
<DESCRIPTION>TWI (Slave) Address Mask Register</DESCRIPTION>
<TEXT>The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BD</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWAM6</NAME>
<ALIAS>TWAMR6</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWAM5</NAME>
<ALIAS>TWAMR5</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWAM4</NAME>
<ALIAS>TWAMR4</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWAM3</NAME>
<ALIAS>TWAMR3</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWAM2</NAME>
<ALIAS>TWAMR2</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWAM1</NAME>
<ALIAS>TWAMR1</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWAM0</NAME>
<ALIAS>TWAMR0</ALIAS>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</TWAMR>
<TWBR>
<NAME>TWBR</NAME>
<DESCRIPTION>TWI Bit Rate register</DESCRIPTION>
<TEXT>TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B8</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWBR7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWBR6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWBR5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWBR4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWBR3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWBR2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWBR1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWBR0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWBR>
<TWCR>
<NAME>TWCR</NAME>
<DESCRIPTION>TWI Control Register</DESCRIPTION>
<TEXT>The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BC</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWINT</NAME>
<DESCRIPTION>TWI Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWEA</NAME>
<DESCRIPTION>TWI Enable Acknowledge Bit</DESCRIPTION>
<TEXT>The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWSTA</NAME>
<DESCRIPTION>TWI Start Condition Bit</DESCRIPTION>
<TEXT>The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWSTO</NAME>
<DESCRIPTION>TWI Stop Condition Bit</DESCRIPTION>
<TEXT>Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWWC</NAME>
<DESCRIPTION>TWI Write Collition Flag</DESCRIPTION>
<TEXT>The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWEN</NAME>
<DESCRIPTION>TWI Enable Bit</DESCRIPTION>
<TEXT>The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT0>
<NAME>TWIE</NAME>
<DESCRIPTION>TWI Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWCR>
<TWSR>
<NAME>TWSR</NAME>
<DESCRIPTION>TWI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B9</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWS7</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWS6</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWS5</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWS4</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWS3</NAME>
<DESCRIPTION>TWI Status</DESCRIPTION>
<TEXT>Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT1>
<NAME>TWPS1</NAME>
<DESCRIPTION>TWI Prescaler</DESCRIPTION>
<TEXT>Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWPS0</NAME>
<DESCRIPTION>TWI Prescaler</DESCRIPTION>
<TEXT>Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWSR>
<TWDR>
<NAME>TWDR</NAME>
<DESCRIPTION>TWI Data register</DESCRIPTION>
<TEXT>In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BB</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TWD7</NAME>
<DESCRIPTION>TWI Data Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWD6</NAME>
<DESCRIPTION>TWI Data Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWD5</NAME>
<DESCRIPTION>TWI Data Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWD4</NAME>
<DESCRIPTION>TWI Data Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWD3</NAME>
<DESCRIPTION>TWI Data Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWD2</NAME>
<DESCRIPTION>TWI Data Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWD1</NAME>
<DESCRIPTION>TWI Data Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWD0</NAME>
<DESCRIPTION>TWI Data Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</TWDR>
<TWAR>
<NAME>TWAR</NAME>
<DESCRIPTION>TWI (Slave) Address register</DESCRIPTION>
<TEXT>The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$BA</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TWA6</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TWA5</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TWA4</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TWA3</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TWA2</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TWA1</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TWA0</NAME>
<DESCRIPTION>TWI (Slave) Address register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TWGCE</NAME>
<DESCRIPTION>TWI General Call Recognition Enable Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TWAR>
</TWI>
<SPI>
<LIST>[SPDR:SPSR:SPCR]</LIST>
<LINK/>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)</TEXT>
<SPCR>
<NAME>SPCR</NAME>
<DESCRIPTION>SPI Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2C</IO_ADDR>
<MEM_ADDR>$4C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIE</NAME>
<DESCRIPTION>SPI Interrupt Enable</DESCRIPTION>
<TEXT>This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPE</NAME>
<DESCRIPTION>SPI Enable</DESCRIPTION>
<TEXT>When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DORD</NAME>
<DESCRIPTION>Data Order</DESCRIPTION>
<TEXT>When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MSTR</NAME>
<DESCRIPTION>Master/Slave Select</DESCRIPTION>
<TEXT>This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CPOL</NAME>
<DESCRIPTION>Clock polarity</DESCRIPTION>
<TEXT>When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CPHA</NAME>
<DESCRIPTION>Clock Phase</DESCRIPTION>
<TEXT>Refer to Figure 36 or Figure 37 for the functionality of this bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPR1</NAME>
<DESCRIPTION>SPI Clock Rate Select 1</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPR0</NAME>
<DESCRIPTION>SPI Clock Rate Select 0</DESCRIPTION>
<TEXT>These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPCR>
<SPSR>
<NAME>SPSR</NAME>
<DESCRIPTION>SPI Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$2D</IO_ADDR>
<MEM_ADDR>$4D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPIF</NAME>
<DESCRIPTION>SPI Interrupt Flag</DESCRIPTION>
<TEXT>When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WCOL</NAME>
<DESCRIPTION>Write Collision Flag</DESCRIPTION>
<TEXT>The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT0>
<NAME>SPI2X</NAME>
<DESCRIPTION>Double SPI Speed Bit</DESCRIPTION>
<TEXT>When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPSR>
<SPDR>
<NAME>SPDR</NAME>
<DESCRIPTION>SPI Data Register</DESCRIPTION>
<TEXT>The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.</TEXT>
<IO_ADDR>$2E</IO_ADDR>
<MEM_ADDR>$4E</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SPDR7</NAME>
<DESCRIPTION>SPI Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SPDR6</NAME>
<DESCRIPTION>SPI Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SPDR5</NAME>
<DESCRIPTION>SPI Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SPDR4</NAME>
<DESCRIPTION>SPI Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SPDR3</NAME>
<DESCRIPTION>SPI Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SPDR2</NAME>
<DESCRIPTION>SPI Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SPDR1</NAME>
<DESCRIPTION>SPI Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPDR0</NAME>
<DESCRIPTION>SPI Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPDR>
</SPI>
<PORTA>
<LIST>[PORTA:DDRA:PINA]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTA>
<NAME>PORTA</NAME>
<DESCRIPTION>Port A Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$02</IO_ADDR>
<MEM_ADDR>$22</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTA7</NAME>
<DESCRIPTION>Port A Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTA6</NAME>
<DESCRIPTION>Port A Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTA5</NAME>
<DESCRIPTION>Port A Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTA4</NAME>
<DESCRIPTION>Port A Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTA3</NAME>
<DESCRIPTION>Port A Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTA2</NAME>
<DESCRIPTION>Port A Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTA1</NAME>
<DESCRIPTION>Port A Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTA0</NAME>
<DESCRIPTION>Port A Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTA>
<DDRA>
<NAME>DDRA</NAME>
<DESCRIPTION>Port A Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$01</IO_ADDR>
<MEM_ADDR>$21</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDA7</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDA6</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDA5</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDA4</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDA3</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDA2</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDA1</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDA0</NAME>
<DESCRIPTION>Data Direction Register, Port A, bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRA>
<PINA>
<NAME>PINA</NAME>
<DESCRIPTION>Port A Input Pins</DESCRIPTION>
<TEXT>The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$00</IO_ADDR>
<MEM_ADDR>$20</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINA7</NAME>
<DESCRIPTION>Input Pins, Port A bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINA6</NAME>
<DESCRIPTION>Input Pins, Port A bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINA5</NAME>
<DESCRIPTION>Input Pins, Port A bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINA4</NAME>
<DESCRIPTION>Input Pins, Port A bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINA3</NAME>
<DESCRIPTION>Input Pins, Port A bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINA2</NAME>
<DESCRIPTION>Input Pins, Port A bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINA1</NAME>
<DESCRIPTION>Input Pins, Port A bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINA0</NAME>
<DESCRIPTION>Input Pins, Port A bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>Hi-Z</INIT_VAL>
</BIT0>
</PINA>
</PORTA>
<PORTB>
<LIST>[PORTB:DDRB:PINB]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTB>
<NAME>PORTB</NAME>
<DESCRIPTION>Port B Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$05</IO_ADDR>
<MEM_ADDR>$25</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTB7</NAME>
<DESCRIPTION>Port B Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTB6</NAME>
<DESCRIPTION>Port B Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTB5</NAME>
<DESCRIPTION>Port B Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTB4</NAME>
<DESCRIPTION>Port B Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTB3</NAME>
<DESCRIPTION>Port B Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTB2</NAME>
<DESCRIPTION>Port B Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTB1</NAME>
<DESCRIPTION>Port B Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTB0</NAME>
<DESCRIPTION>Port B Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTB>
<DDRB>
<NAME>DDRB</NAME>
<DESCRIPTION>Port B Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$04</IO_ADDR>
<MEM_ADDR>$24</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDB7</NAME>
<DESCRIPTION>Port B Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDB6</NAME>
<DESCRIPTION>Port B Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDB5</NAME>
<DESCRIPTION>Port B Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDB4</NAME>
<DESCRIPTION>Port B Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDB3</NAME>
<DESCRIPTION>Port B Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDB2</NAME>
<DESCRIPTION>Port B Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDB1</NAME>
<DESCRIPTION>Port B Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDB0</NAME>
<DESCRIPTION>Port B Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRB>
<PINB>
<NAME>PINB</NAME>
<DESCRIPTION>Port B Input Pins</DESCRIPTION>
<TEXT>The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$03</IO_ADDR>
<MEM_ADDR>$23</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINB7</NAME>
<DESCRIPTION>Port B Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINB6</NAME>
<DESCRIPTION>Port B Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINB5</NAME>
<DESCRIPTION>Port B Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINB4</NAME>
<DESCRIPTION>Port B Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINB3</NAME>
<DESCRIPTION>Port B Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINB2</NAME>
<DESCRIPTION>Port B Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINB1</NAME>
<DESCRIPTION>Port B Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINB0</NAME>
<DESCRIPTION>Port B Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINB>
</PORTB>
<PORTC>
<LIST>[PORTC:DDRC:PINC]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTC>
<NAME>PORTC</NAME>
<DESCRIPTION>Port C Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$08</IO_ADDR>
<MEM_ADDR>$28</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTC7</NAME>
<DESCRIPTION>Port C Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTC6</NAME>
<DESCRIPTION>Port C Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTC5</NAME>
<DESCRIPTION>Port C Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTC4</NAME>
<DESCRIPTION>Port C Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTC3</NAME>
<DESCRIPTION>Port C Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTC2</NAME>
<DESCRIPTION>Port C Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTC1</NAME>
<DESCRIPTION>Port C Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTC0</NAME>
<DESCRIPTION>Port C Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTC>
<DDRC>
<NAME>DDRC</NAME>
<DESCRIPTION>Port C Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$07</IO_ADDR>
<MEM_ADDR>$27</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDC7</NAME>
<DESCRIPTION>Port C Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDC6</NAME>
<DESCRIPTION>Port C Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDC5</NAME>
<DESCRIPTION>Port C Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDC4</NAME>
<DESCRIPTION>Port C Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDC3</NAME>
<DESCRIPTION>Port C Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDC2</NAME>
<DESCRIPTION>Port C Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDC1</NAME>
<DESCRIPTION>Port C Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDC0</NAME>
<DESCRIPTION>Port C Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRC>
<PINC>
<NAME>PINC</NAME>
<DESCRIPTION>Port C Input Pins</DESCRIPTION>
<TEXT>The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$06</IO_ADDR>
<MEM_ADDR>$26</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINC7</NAME>
<DESCRIPTION>Port C Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINC6</NAME>
<DESCRIPTION>Port C Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINC5</NAME>
<DESCRIPTION>Port C Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINC4</NAME>
<DESCRIPTION>Port C Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINC3</NAME>
<DESCRIPTION>Port C Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINC2</NAME>
<DESCRIPTION>Port C Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINC1</NAME>
<DESCRIPTION>Port C Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINC0</NAME>
<DESCRIPTION>Port C Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINC>
</PORTC>
<PORTD>
<LIST>[PORTD:DDRD:PIND]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTD>
<NAME>PORTD</NAME>
<DESCRIPTION>Port D Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0B</IO_ADDR>
<MEM_ADDR>$2B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTD7</NAME>
<DESCRIPTION>Port D Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTD6</NAME>
<DESCRIPTION>Port D Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTD5</NAME>
<DESCRIPTION>Port D Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTD4</NAME>
<DESCRIPTION>Port D Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTD3</NAME>
<DESCRIPTION>Port D Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTD2</NAME>
<DESCRIPTION>Port D Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTD1</NAME>
<DESCRIPTION>Port D Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTD0</NAME>
<DESCRIPTION>Port D Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTD>
<DDRD>
<NAME>DDRD</NAME>
<DESCRIPTION>Port D Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0A</IO_ADDR>
<MEM_ADDR>$2A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDD7</NAME>
<DESCRIPTION>Port D Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDD6</NAME>
<DESCRIPTION>Port D Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDD5</NAME>
<DESCRIPTION>Port D Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDD4</NAME>
<DESCRIPTION>Port D Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDD3</NAME>
<DESCRIPTION>Port D Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDD2</NAME>
<DESCRIPTION>Port D Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDD1</NAME>
<DESCRIPTION>Port D Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDD0</NAME>
<DESCRIPTION>Port D Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRD>
<PIND>
<NAME>PIND</NAME>
<DESCRIPTION>Port D Input Pins</DESCRIPTION>
<TEXT>The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.</TEXT>
<IO_ADDR>$09</IO_ADDR>
<MEM_ADDR>$29</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PIND7</NAME>
<DESCRIPTION>Port D Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PIND6</NAME>
<DESCRIPTION>Port D Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PIND5</NAME>
<DESCRIPTION>Port D Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PIND4</NAME>
<DESCRIPTION>Port D Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PIND3</NAME>
<DESCRIPTION>Port D Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PIND2</NAME>
<DESCRIPTION>Port D Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PIND1</NAME>
<DESCRIPTION>Port D Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PIND0</NAME>
<DESCRIPTION>Port D Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PIND>
</PORTD>
<PORTE>
<LIST>[PORTE:DDRE:PINE]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTE>
<NAME>PORTE</NAME>
<DESCRIPTION>Data Register, Port E</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0E</IO_ADDR>
<MEM_ADDR>$2E</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTE7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTE6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTE5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTE4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTE3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTE>
<DDRE>
<NAME>DDRE</NAME>
<DESCRIPTION>Data Direction Register, Port E</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0D</IO_ADDR>
<MEM_ADDR>$2D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDE7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDE6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDE5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDE4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDE3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRE>
<PINE>
<NAME>PINE</NAME>
<DESCRIPTION>Input Pins, Port E</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0C</IO_ADDR>
<MEM_ADDR>$2C</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINE7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINE6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINE5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINE4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINE3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINE2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINE1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINE0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINE>
</PORTE>
<PORTF>
<LIST>[PORTF:DDRF:PINF]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTF>
<NAME>PORTF</NAME>
<DESCRIPTION>Data Register, Port F</DESCRIPTION>
<TEXT/>
<IO_ADDR>$11</IO_ADDR>
<MEM_ADDR>$31</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTF7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTF6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTF5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTF4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTF3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTF2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTF1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTF0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTF>
<DDRF>
<NAME>DDRF</NAME>
<DESCRIPTION>Data Direction Register, Port F</DESCRIPTION>
<TEXT/>
<IO_ADDR>$10</IO_ADDR>
<MEM_ADDR>$30</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDF7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDF6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDF5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDF4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDF3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDF2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDF1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDF0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRF>
<PINF>
<NAME>PINF</NAME>
<DESCRIPTION>Input Pins, Port F</DESCRIPTION>
<TEXT/>
<IO_ADDR>$0F</IO_ADDR>
<MEM_ADDR>$2F</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINF7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINF6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINF5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINF4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINF3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINF2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINF1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINF0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINF>
</PORTF>
<PORTG>
<LIST>[PORTG:DDRG:PING]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTG>
<NAME>PORTG</NAME>
<DESCRIPTION>Data Register, Port G</DESCRIPTION>
<TEXT/>
<IO_ADDR>$14</IO_ADDR>
<MEM_ADDR>$34</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PORTG5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTG4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTG3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTG2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTG1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTG0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTG>
<DDRG>
<NAME>DDRG</NAME>
<DIRECTION>Data Direction Register, Port G</DIRECTION>
<TEXT/>
<IO_ADDR>$13</IO_ADDR>
<MEM_ADDR>$33</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>DDG5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDG4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDG3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDG2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDG1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDG0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRG>
<PING>
<NAME>PING</NAME>
<DESCRIPTION>Input Pins, Port G</DESCRIPTION>
<TEXT/>
<IO_ADDR>$12</IO_ADDR>
<MEM_ADDR>$32</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT5>
<NAME>PING5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PING4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PING3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PING2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PING1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PING0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PING>
</PORTG>
<PORTH>
<LIST>[PORTH:DDRH:PINH]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTH>
<NAME>PORTH</NAME>
<DESCRIPTION>PORT H Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$102</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTH7</NAME>
<DESCRIPTION>PORT H Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTH6</NAME>
<DESCRIPTION>PORT H Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTH5</NAME>
<DESCRIPTION>PORT H Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTH4</NAME>
<DESCRIPTION>PORT H Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTH3</NAME>
<DESCRIPTION>PORT H Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTH2</NAME>
<DESCRIPTION>PORT H Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTH1</NAME>
<DESCRIPTION>PORT H Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTH0</NAME>
<DESCRIPTION>PORT H Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTH>
<DDRH>
<NAME>DDRH</NAME>
<DESCRIPTION>PORT H Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$101</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDH7</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDH6</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDH5</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDH4</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDH3</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDH2</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDH1</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDH0</NAME>
<DESCRIPTION>PORT H Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRH>
<PINH>
<NAME>PINH</NAME>
<DESCRIPTION>PORT H Input Pins</DESCRIPTION>
<TEXT>The PORT H Input Pins address - PINH - is not a register, and this address enables access to the physical value on each PORT H pin. When reading PORTH, the PORT H Data Latch is read, and when reading PINH, the logical values present on the pins are read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$100</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINH7</NAME>
<DESCRIPTION>PORT H Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINH6</NAME>
<DESCRIPTION>PORT H Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINH5</NAME>
<DESCRIPTION>PORT H Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINH4</NAME>
<DESCRIPTION>PORT H Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINH3</NAME>
<DESCRIPTION>PORT H Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINH2</NAME>
<DESCRIPTION>PORT H Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINH1</NAME>
<DESCRIPTION>PORT H Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINH0</NAME>
<DESCRIPTION>PORT H Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINH>
</PORTH>
<PORTJ>
<LIST>[PORTJ:DDRJ:PINJ]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTJ>
<NAME>PORTJ</NAME>
<DESCRIPTION>PORT J Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$105</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTJ7</NAME>
<DESCRIPTION>PORT J Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTJ6</NAME>
<DESCRIPTION>PORT J Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTJ5</NAME>
<DESCRIPTION>PORT J Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTJ4</NAME>
<DESCRIPTION>PORT J Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTJ3</NAME>
<DESCRIPTION>PORT J Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTJ2</NAME>
<DESCRIPTION>PORT J Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTJ1</NAME>
<DESCRIPTION>PORT J Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTJ0</NAME>
<DESCRIPTION>PORT J Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTJ>
<DDRJ>
<NAME>DDRJ</NAME>
<DESCRIPTION>PORT J Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$104</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDJ7</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDJ6</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDJ5</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDJ4</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDJ3</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDJ2</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDJ1</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDJ0</NAME>
<DESCRIPTION>PORT J Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRJ>
<PINJ>
<NAME>PINJ</NAME>
<DESCRIPTION>PORT J Input Pins</DESCRIPTION>
<TEXT>The PORT J Input Pins address - PINJ - is not a register, and this address enables access to the physical value on each PORT J pin. When reading PORTJ, the PORT J Data Latch is read, and when reading PINJ, the logical values present on the pins are read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$103</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINJ7</NAME>
<DESCRIPTION>PORT J Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINJ6</NAME>
<DESCRIPTION>PORT J Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINJ5</NAME>
<DESCRIPTION>PORT J Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINJ4</NAME>
<DESCRIPTION>PORT J Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINJ3</NAME>
<DESCRIPTION>PORT J Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINJ2</NAME>
<DESCRIPTION>PORT J Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINJ1</NAME>
<DESCRIPTION>PORT J Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINJ0</NAME>
<DESCRIPTION>PORT J Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINJ>
</PORTJ>
<PORTK>
<LIST>[PORTK:DDRK:PINK]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTK>
<NAME>PORTK</NAME>
<DESCRIPTION>PORT K Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$108</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTK7</NAME>
<DESCRIPTION>PORT K Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTK6</NAME>
<DESCRIPTION>PORT K Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTK5</NAME>
<DESCRIPTION>PORT K Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTK4</NAME>
<DESCRIPTION>PORT K Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTK3</NAME>
<DESCRIPTION>PORT K Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTK2</NAME>
<DESCRIPTION>PORT K Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTK1</NAME>
<DESCRIPTION>PORT K Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTK0</NAME>
<DESCRIPTION>PORT K Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTK>
<DDRK>
<NAME>DDRK</NAME>
<DESCRIPTION>PORT K Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$107</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDK7</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDK6</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDK5</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDK4</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDK3</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDK2</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDK1</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDK0</NAME>
<DESCRIPTION>PORT K Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRK>
<PINK>
<NAME>PINK</NAME>
<DESCRIPTION>PORT K Input Pins</DESCRIPTION>
<TEXT>The PORT K Input Pins address - PINK - is not a register, and this address enables access to the physical value on each PORT K pin. When reading PORTK, the PORT K Data Latch is read, and when reading PINK, the logical values present on the pins are read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$106</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINK7</NAME>
<DESCRIPTION>PORT K Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINK6</NAME>
<DESCRIPTION>PORT K Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINK5</NAME>
<DESCRIPTION>PORT K Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINK4</NAME>
<DESCRIPTION>PORT K Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINK3</NAME>
<DESCRIPTION>PORT K Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINK2</NAME>
<DESCRIPTION>PORT K Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINK1</NAME>
<DESCRIPTION>PORT K Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINK0</NAME>
<DESCRIPTION>PORT K Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINK>
</PORTK>
<PORTL>
<LIST>[PORTL:DDRL:PINL]</LIST>
<LINK/>
<ICON>io_port.bmp</ICON>
<ID>AVRSimIOPort.SimIOPort</ID>
<TEXT/>
<PORTL>
<NAME>PORTL</NAME>
<DESCRIPTION>PORT L Data Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$10B</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PORTL7</NAME>
<DESCRIPTION>PORT L Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PORTL6</NAME>
<DESCRIPTION>PORT L Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PORTL5</NAME>
<DESCRIPTION>PORT L Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PORTL4</NAME>
<DESCRIPTION>PORT L Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PORTL3</NAME>
<DESCRIPTION>PORT L Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PORTL2</NAME>
<DESCRIPTION>PORT L Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PORTL1</NAME>
<DESCRIPTION>PORT L Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORTL0</NAME>
<DESCRIPTION>PORT L Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PORTL>
<DDRL>
<NAME>DDRL</NAME>
<DESCRIPTION>PORT L Data Direction Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$10A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>DDL7</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>DDL6</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>DDL5</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>DDL4</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DDL3</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>DDL2</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>DDL1</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>DDL0</NAME>
<DESCRIPTION>PORT L Data Direction Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DDRL>
<PINL>
<NAME>PINL</NAME>
<DESCRIPTION>PORT L Input Pins</DESCRIPTION>
<TEXT>The PORT L Input Pins address - PINL - is not a register, and this address enables access to the physical value on each PORT L pin. When reading PORTL, the PORT L Data Latch is read, and when reading PINL, the logical values present on the pins are read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$109</MEM_ADDR>
<ICON>io_port.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PINL7</NAME>
<DESCRIPTION>PORT L Input Pins bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PINL6</NAME>
<DESCRIPTION>PORT L Input Pins bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PINL5</NAME>
<DESCRIPTION>PORT L Input Pins bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PINL4</NAME>
<DESCRIPTION>PORT L Input Pins bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PINL3</NAME>
<DESCRIPTION>PORT L Input Pins bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PINL2</NAME>
<DESCRIPTION>PORT L Input Pins bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PINL1</NAME>
<DESCRIPTION>PORT L Input Pins bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PINL0</NAME>
<DESCRIPTION>PORT L Input Pins bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PINL>
</PORTL>
<TIMER_COUNTER_0>
<LIST>[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>At8pwm0_01</ID>
<TEXT/>
<OCR0B>
<NAME>OCR0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$28</IO_ADDR>
<MEM_ADDR>$48</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR0B_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR0B_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR0B_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR0B_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR0B_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR0B_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR0B_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR0B_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0B>
<OCR0A>
<NAME>OCR0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Register</DESCRIPTION>
<TEXT>The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.</TEXT>
<IO_ADDR>$27</IO_ADDR>
<MEM_ADDR>$47</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCROA_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCROA_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCROA_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCROA_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCROA_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCROA_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCROA_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCROA_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR0A>
<TCNT0>
<NAME>TCNT0</NAME>
<DESCRIPTION>Timer/Counter0</DESCRIPTION>
<TEXT>The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.</TEXT>
<IO_ADDR>$26</IO_ADDR>
<MEM_ADDR>$46</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT0_7</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT0_6</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT0_5</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT0_4</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT0_3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT0_2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT0_1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT0_0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT0>
<TCCR0B>
<NAME>TCCR0B</NAME>
<DESCRIPTION>Timer/Counter Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>$25</IO_ADDR>
<MEM_ADDR>$45</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC0A</NAME>
<DESCRIPTION>Force Output Compare A</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC0B</NAME>
<DESCRIPTION>Force Output Compare B</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>WGM02</NAME>
<DESCRIPTION/>
<TEXT/>
<ACESS>RW</ACESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS02</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS01</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS00</NAME>
<DESCRIPTION>Clock Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0B>
<TCCR0A>
<NAME>TCCR0A</NAME>
<DESCRIPTION>Timer/Counter Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>$24</IO_ADDR>
<MEM_ADDR>$44</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM0A1</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM0A0</NAME>
<DESCRIPTION>Compare Output Mode, Phase Correct PWM Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM0B1</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM0B0</NAME>
<DESCRIPTION>Compare Output Mode, Fast PWm</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM01</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM00</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR0A>
<TIMSK0>
<NAME>TIMSK0</NAME>
<DESCRIPTION>Timer/Counter0 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6E</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCIE0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match B Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Match A Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK0>
<TIFR0>
<NAME>TIFR0</NAME>
<DESCRIPTION>Timer/Counter0 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$15</IO_ADDR>
<MEM_ADDR>$35</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCF0B</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0B</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF0A</NAME>
<DESCRIPTION>Timer/Counter0 Output Compare Flag 0A</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV0</NAME>
<DESCRIPTION>Timer/Counter0 Overflow Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR0>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer/Counter Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT>Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT0>
<NAME>PSRSYNC</NAME>
<ALIAS>PSR10</ALIAS>
<DESCRIPTION>Prescaler Reset Timer/Counter1 and Timer/Counter0</DESCRIPTION>
<TEXT>When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GTCCR>
</TIMER_COUNTER_0>
<TIMER_COUNTER_2>
<LIST>[TIMSK2:TIFR2:TCCR2A:TCCR2B:TCNT2:OCR2A:OCR2B:ASSR:GTCCR]</LIST>
<LINK/>
<ICON>io_timer.bmp</ICON>
<ID>At8pwm2_07</ID>
<TEXT>The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls</TEXT>
<TIMSK2>
<NAME>TIMSK2</NAME>
<DESCRIPTION>Timer/Counter Interrupt Mask register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$70</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCIE2B</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Match B Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE2A</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Match A Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE2</NAME>
<ALIAS>TOIE2A</ALIAS>
<DESCRIPTION>Timer/Counter2 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK2>
<TIFR2>
<NAME>TIFR2</NAME>
<DESCRIPTION>Timer/Counter Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$17</IO_ADDR>
<MEM_ADDR>$37</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>OCF2B</NAME>
<DESCRIPTION>Output Compare Flag 2B</DESCRIPTION>
<TEXT>The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF2A</NAME>
<DESCRIPTION>Output Compare Flag 2A</DESCRIPTION>
<TEXT>The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV2</NAME>
<DESCRIPTION>Timer/Counter2 Overflow Flag</DESCRIPTION>
<TEXT>The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR2>
<TCCR2A>
<NAME>TCCR2A</NAME>
<DESCRIPTION>Timer/Counter2 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B0</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM2A1</NAME>
<DESCRIPTION>Compare Output Mode bit 1</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM2A0</NAME>
<DESCRIPTION>Compare Output Mode bit 1</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM2B1</NAME>
<DESCRIPTION>Compare Output Mode bit 1</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM2B0</NAME>
<DESCRIPTION>Compare Output Mode bit 0</DESCRIPTION>
<TEXT>The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functio</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>WGM21</NAME>
<DESCRIPTION>Waveform Genration Mode</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM20</NAME>
<DESCRIPTION>Waveform Genration Mode</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR2A>
<TCCR2B>
<NAME>TCCR2B</NAME>
<DESCRIPTION>Timer/Counter2 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B1</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC2A</NAME>
<DESCRIPTION>Force Output Compare A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC2B</NAME>
<DESCRIPTION>Force Output Compare B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>WGM22</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS22</NAME>
<DESCRIPTION>Clock Select bit 2</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS21</NAME>
<DESCRIPTION>Clock Select bit 1</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS20</NAME>
<DESCRIPTION>Clock Select bit 0</DESCRIPTION>
<TEXT>The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR2B>
<TCNT2>
<NAME>TCNT2</NAME>
<DESCRIPTION>Timer/Counter2</DESCRIPTION>
<TEXT>This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B2</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT2-7</NAME>
<DESCRIPTION>Timer/Counter 2 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT2-6</NAME>
<DESCRIPTION>Timer/Counter 2 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT2-5</NAME>
<DESCRIPTION>Timer/Counter 2 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT2-4</NAME>
<DESCRIPTION>Timer/Counter 2 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT2-3</NAME>
<DESCRIPTION>Timer/Counter 2 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT2-2</NAME>
<DESCRIPTION>Timer/Counter 2 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT2-1</NAME>
<DESCRIPTION>Timer/Counter 2 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT2-0</NAME>
<DESCRIPTION>Timer/Counter 2 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT2>
<OCR2B>
<NAME>OCR2B</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register B</DESCRIPTION>
<TEXT>The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B4</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2-7</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2-6</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2-5</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2-4</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2-3</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2-2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2-1</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2-0</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2B>
<OCR2A>
<NAME>OCR2A</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register A</DESCRIPTION>
<TEXT>The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B3</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR2-7</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR2-6</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR2-5</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR2-4</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2-3</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2-2</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR2-1</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR2-0</NAME>
<DESCRIPTION>Timer/Counter2 Output Compare Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR2A>
<ASSR>
<NAME>ASSR</NAME>
<DESCRIPTION>Asynchronous Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$B6</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>EXCLK</NAME>
<DESCRIPTION>Enable External Clock Input</DESCRIPTION>
<TEXT>When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>AS2</NAME>
<DESCRIPTION>Asynchronous Timer/Counter2</DESCRIPTION>
<TEXT>When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCN2UB</NAME>
<DESCRIPTION>Timer/Counter2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR2AUB</NAME>
<DESCRIPTION>Output Compare Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR2BUB</NAME>
<DESCRIPTION>Output Compare Register 2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCR2AUB</NAME>
<DESCRIPTION>Timer/Counter Control Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCR2BUB</NAME>
<DESCRIPTION>Timer/Counter Control Register2 Update Busy</DESCRIPTION>
<TEXT>When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ASSR>
<GTCCR>
<NAME>GTCCR</NAME>
<DESCRIPTION>General Timer Counter Control register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$23</IO_ADDR>
<MEM_ADDR>$43</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>TSM</NAME>
<DESCRIPTION>Timer/Counter Synchronization Mode</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT1>
<NAME>PSRASY</NAME>
<ALIAS>PSR2</ALIAS>
<DESCRIPTION>Prescaler Reset Timer/Counter2</DESCRIPTION>
<TEXT>When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 107 for a description of the Timer/Counter Synchronization mode.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
</GTCCR>
</TIMER_COUNTER_2>
<WATCHDOG>
<LIST>[WDTCSR]</LIST>
<LINK/>
<ICON>io_watch.bmp</ICON>
<ID/>
<TEXT/>
<WDTCSR>
<NAME>WDTCSR</NAME>
<DESCRIPTION>Watchdog Timer Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$60</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>WDIF</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Flag</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>WDIE</NAME>
<DESCRIPTION>Watchdog Timeout Interrupt Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>WDP3</NAME>
<DESCRIPTION>Watchdog Timer Prescaler Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>WDCE</NAME>
<DESCRIPTION>Watchdog Change Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDE</NAME>
<DESCRIPTION>Watch Dog Enable</DESCRIPTION>
<TEXT>When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>WDP2</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WDP1</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WDP0</NAME>
<DESCRIPTION>Watch Dog Timer Prescaler bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</WDTCSR>
</WATCHDOG>
<USART1>
<LIST>[UDR1:UCSR1A:UCSR1B:UCSR1C:UBRR1H:UBRR1L]</LIST>
<LINK>[UBRR1H:UBRR1L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica</TEXT>
<UDR1>
<NAME>UDR1</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR1 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CE</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR1-7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR1-6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR1-5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR1-4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR1-3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR1-2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR1-1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR1-0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR1>
<UCSR1A>
<NAME>UCSR1A</NAME>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C8</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC1</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC1</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE1</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE1</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR1</NAME>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE1</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X1</NAME>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM1</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1A>
<UCSR1B>
<NAME>UCSR1B</NAME>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$C9</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE1</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE1</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE1</NAME>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN1</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN1</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ12</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB81</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB81</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1B>
<UCSR1C>
<NAME>UCSR1C</NAME>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CA</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UMSEL11</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL10</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM11</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM10</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS1</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ11</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ10</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL1</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR1C>
<UBRR1H>
<NAME>UBRR1H</NAME>
<DESCRIPTION>USART Baud Rate Register High Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CD</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR1H>
<UBRR1L>
<NAME>UBRR1L</NAME>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$CC</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR1L>
</USART1>
<EEPROM>
<LIST>[EEARH:EEARL:EEDR:EECR]</LIST>
<LINK/>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT>EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute</TEXT>
<EEARH>
<NAME>EEARH</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$22</IO_ADDR>
<MEM_ADDR>$42</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>EEAR11</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR10</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR9</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR8</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARH>
<EEARL>
<NAME>EEARL</NAME>
<DESCRIPTION>EEPROM Address Register Low Byte</DESCRIPTION>
<TEXT>Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. </TEXT>
<IO_ADDR>$21</IO_ADDR>
<MEM_ADDR>$41</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEAR7</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEAR6</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEAR5</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEAR4</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEAR3</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEAR2</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEAR1</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEAR0</NAME>
<DESCRIPTION>EEPROM Read/Write Access Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEARL>
<EEDR>
<NAME>EEDR</NAME>
<DESCRIPTION>EEPROM Data Register</DESCRIPTION>
<TEXT>For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.</TEXT>
<IO_ADDR>$20</IO_ADDR>
<MEM_ADDR>$40</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>EEDR7</NAME>
<DESCRIPTION>EEPROM Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>EEDR6</NAME>
<DESCRIPTION>EEPROM Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>EEDR5</NAME>
<DESCRIPTION>EEPROM Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEDR4</NAME>
<DESCRIPTION>EEPROM Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EEDR3</NAME>
<DESCRIPTION>EEPROM Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEDR2</NAME>
<DESCRIPTION>EEPROM Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEDR1</NAME>
<DESCRIPTION>EEPROM Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EEDR0</NAME>
<DESCRIPTION>EEPROM Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EEDR>
<EECR>
<NAME>EECR</NAME>
<DESCRIPTION>EEPROM Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1F</IO_ADDR>
<MEM_ADDR>$3F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>EEPM1</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 1</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT5>
<BIT4>
<NAME>EEPM0</NAME>
<DESCRIPTION>EEPROM Programming Mode Bit 0</DESCRIPTION>
<TEXT>The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT4>
<BIT3>
<NAME>EERIE</NAME>
<DESCRIPTION>EEPROM Ready Interrupt Enable</DESCRIPTION>
<TEXT>EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>EEMPE</NAME>
<DESCRIPTION>EEPROM Master Write Enable</DESCRIPTION>
<TEXT>The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EEPE</NAME>
<DESCRIPTION>EEPROM Write Enable</DESCRIPTION>
<TEXT>The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>X</INIT_VAL>
</BIT1>
<BIT0>
<NAME>EERE</NAME>
<DESCRIPTION>EEPROM Read Enable</DESCRIPTION>
<TEXT>The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EECR>
</EEPROM>
<TIMER_COUNTER_5>
<LIST>[TIMSK5:TIFR5:TCCR5A:TCCR5B:TCCR5C:TCNT5H:TCNT5L:OCR5AH:OCR5AL:OCR5BH:OCR5BL:ICR5H:ICR5L:OCR5CH:OCR5CL]</LIST>
<LINK>[TCNT5H:TCNT5L];[OCR5AH:OCR5AL];[OCR5BH:OCR5BL];[OCR5CH:OCR5CL];[ICR5H:ICR3L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm5_00.xml</ID>
<TEXT/>
<TCCR5A>
<NAME>TCCR5A</NAME>
<DESCRIPTION>Timer/Counter5 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$120</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM5A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM5A1 and COM5A0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM5A0</NAME>
<DESCRIPTION>Compare Output Mode 5A, bit 0</DESCRIPTION>
<TEXT>The COM5A1 and COM5A0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM5B1</NAME>
<DESCRIPTION>Compare Output Mode 5B, bit 1</DESCRIPTION>
<TEXT>The COM5B1 and COM5B0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM5B0</NAME>
<DESCRIPTION>Compare Output Mode 5B, bit 0</DESCRIPTION>
<TEXT>The COM5B1 and COM5B0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>COM5C1</NAME>
<DESCRIPTION>Compare Output Mode 5C, bit 1</DESCRIPTION>
<TEXT>The COM5C1 and COM5C0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>COM5C0</NAME>
<DESCRIPTION>Compare Output Mode 5C, bit 0</DESCRIPTION>
<TEXT>The COM5C1 and COM5C0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WGM51</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM50</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR5A>
<TCCR5B>
<NAME>TCCR5B</NAME>
<DESCRIPTION>Timer/Counter5 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$121</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC5</NAME>
<DESCRIPTION>Input Capture 5 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC5 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC5 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES5 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES5</NAME>
<DESCRIPTION>Input Capture 5 Edge Select</DESCRIPTION>
<TEXT>While the ICES5 bit is cleared (zero), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the falling edge of the input capture pin - ICP. While the ICES5 bit is set (one), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>WGM53</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM52</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS52</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 5</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T5, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS51</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 5</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T5, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS50</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 5</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR5B>
<TCCR5C>
<NAME>TCCR5C</NAME>
<DESCRIPTION>Timer/Counter 5 Control Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$122</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC5A</NAME>
<DESCRIPTION>Force Output Compare 5A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM5A1 and COM5A0.If the COM5A1 and COM5A0 bits are written in the same cycle as FOC5A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5A1 and COM5A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC5 in TCCR5B is set. The corresponding I/O pin must be set as an output pin for the FOC5A bit to have effect on the pin. The FOC5A bit will always be read as zero. The setting of the FOC5A bit has no effect in PWM m</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC5B</NAME>
<DESCRIPTION>Force Output Compare 5B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM5B1 and COM5B0.If the COM5B1 and COM5B0 bits are written in the same cycle as FOC5B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5B1 and COM5B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC5B bit to have effect on the pin. The FOC5B bit will always be read as zero. The setting of the FOC5B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>FOC5C</NAME>
<DESCRIPTION>Force Output Compare 5C</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM5B1 and COM5B0.If the COM5B1 and COM5B0 bits are written in the same cycle as FOC5B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5B1 and COM5B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC5B bit to have effect on the pin. The FOC5B bit will always be read as zero. The setting of the FOC5B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</TCCR5C>
<TCNT5H>
<NAME>TCNT5H</NAME>
<DESCRIPTION>Timer/Counter5 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter5. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR5A, OCR5B and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$125</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT5H7</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT5H6</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT5H5</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT5H4</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT5H3</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT5H2</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT5H1</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT5H0</NAME>
<DESCRIPTION>Timer/Counter5 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT5H>
<TCNT5L>
<NAME>TCNT5L</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter5. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR5A, OCR5B and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$124</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT5L7</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT5L6</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT5L5</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT5L4</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT5L3</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT5L2</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT5L1</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT5L0</NAME>
<DESCRIPTION>Timer/Counter5 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT5L>
<OCR5AH>
<NAME>OCR5AH</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register A High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interr</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$129</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5AH7</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5AH6</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5AH5</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5AH4</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5AH3</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5AH2</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5AH1</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5AH0</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5AH>
<OCR5AL>
<NAME>OCR5AL</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register A Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$128</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5AL7</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5AL6</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5AL5</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5AL4</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5AL3</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5AL2</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5AL1</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5AL0</NAME>
<DESCRIPTION>Timer/Counter5 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5AL>
<OCR5BH>
<NAME>OCR5BH</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5BH7</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5BH6</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5BH5</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5BH4</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5BH3</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5BH2</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5BH1</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5BH0</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5BH>
<OCR5BL>
<NAME>OCR5BL</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5BL7</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5BL6</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5BL5</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5BL4</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5BL3</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5BL2</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5BL1</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5BL0</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5BL>
<OCR5CH>
<NAME>OCR5CH</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5CH7</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5CH6</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5CH5</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5CH4</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5CH3</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5CH2</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5CH1</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5CH0</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5CH>
<OCR5CL>
<NAME>OCR5CL</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$12C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR5CL7</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR5CL6</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR5CL5</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR5CL4</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR5CL3</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR5CL2</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR5CL1</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR5CL0</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR5CL>
<ICR5H>
<NAME>ICR5H</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES5) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter5 is transferred to the Input Capture Register - ICR5. At the same time, the input capture flag - ICF5 - is set (one). Since the Input Capture Register - ICR5 - is a 16-bit register, a temporary register TEMP is used when ICR5 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR5L, the data is sent to the CPU and the data of the high byte ICR5H is placed in the TEMP register. When the CPU reads the data in the high byte ICR5H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR5L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT5, OCR5A and OCR5B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$127</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR5H7</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR5H6</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR5H5</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR5H4</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR5H3</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR5H2</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR5H1</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR5H0</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR5H>
<ICR5L>
<NAME>ICR5L</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES5) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter5 is transferred to the Input Capture Register - ICR5. At the same time, the input capture flag - ICF5 - is set (one). Since the Input Capture Register - ICR5 - is a 16-bit register, a temporary register TEMP is used when ICR5 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR5L, the data is sent to the CPU and the data of the high byte ICR5H is placed in the TEMP register. When the CPU reads the data in the high byte ICR5H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR5L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT5, OCR5A and OCR5B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$126</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR5L7</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR5L6</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR5L5</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR5L4</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR5L3</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR5L2</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR5L1</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR5L0</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR5L>
<TIMSK5>
<NAME>TIMSK5</NAME>
<DESCRIPTION>Timer/Counter5 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$73</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICIE5</NAME>
<DESCRIPTION>Timer/Counter5 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCIE5C</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare C Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE5C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCIE5B</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare B Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE5B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE5A</NAME>
<DESCRIPTION>Timer/Counter5 Output Compare A Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE5A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter5 occurs, i.e., when the OCF5A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE5</NAME>
<DESCRIPTION>Timer/Counter5 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter5 occurs, i.e., when the TOV5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK5>
<TIFR5>
<NAME>TIFR5</NAME>
<DESCRIPTION>Timer/Counter5 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1A</IO_ADDR>
<MEM_ADDR>$3A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF5</NAME>
<DESCRIPTION>Input Capture Flag 5</DESCRIPTION>
<TEXT>The ICF5 bit is set (one) to flag an input capture event, indicating that the Timer/Counter5 value has been transferred to the input capture register - ICR5. ICF5 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF5 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE5 (Timer/Counter5 Input Capture Interrupt Enable), and ICF5 are set (one), the Timer/Counter5 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCF5C</NAME>
<DESCRIPTION>Output Compare Flag 5C</DESCRIPTION>
<TEXT>The OCF5C bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCF5B</NAME>
<DESCRIPTION>Output Compare Flag 5B</DESCRIPTION>
<TEXT>The OCF5B bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF5A</NAME>
<DESCRIPTION>Output Compare Flag 5A</DESCRIPTION>
<TEXT>The OCF5A bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5A - Output Compare Register 5A. OCF5A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5A (Timer/Counter5 Compare match InterruptA Enable), and the OCF5A are set (one), the Timer/Counter5 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV5</NAME>
<DESCRIPTION>Timer/Counter5 Overflow Flag</DESCRIPTION>
<TEXT>The TOV5 is set (one) when an overflow occurs in Timer/Counter5. TOV5 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV5 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE5 (Timer/Counter5 Overflow Interrupt Enable), and TOV5 are set (one), the Timer/Counter5 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter5 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR5>
</TIMER_COUNTER_5>
<TIMER_COUNTER_4>
<LIST>[TIMSK4:TIFR4:TCCR4A:TCCR4B:TCCR4C:TCNT4H:TCNT4L:OCR4AH:OCR4AL:OCR4BH:OCR4BL:ICR4H:ICR4L:OCR4CH:OCR4CL]</LIST>
<LINK>[TCNT4H:TCNT4L];[OCR4AH:OCR4AL];[OCR4BH:OCR4BL];[OCR4CH:OCR4CL];[ICR4H:ICR4L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm4_00.xml</ID>
<TEXT/>
<TCCR4A>
<NAME>TCCR4A</NAME>
<DESCRIPTION>Timer/Counter4 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A0</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM4A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM4A1 and COM4A0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM4A0</NAME>
<DESCRIPTION>Compare Output Mode 4A, bit 0</DESCRIPTION>
<TEXT>The COM4A1 and COM4A0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM4B1</NAME>
<DESCRIPTION>Compare Output Mode 4B, bit 1</DESCRIPTION>
<TEXT>The COM4B1 and COM4B0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM4B0</NAME>
<DESCRIPTION>Compare Output Mode 4B, bit 0</DESCRIPTION>
<TEXT>The COM4B1 and COM4B0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>COM4C1</NAME>
<DESCRIPTION>Compare Output Mode 4C, bit 1</DESCRIPTION>
<TEXT>The COM4C1 and COM4C0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>COM4C0</NAME>
<DESCRIPTION>Compare Output Mode 4C, bit 0</DESCRIPTION>
<TEXT>The COM4C1 and COM4C0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WGM41</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM40</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR4A>
<TCCR4B>
<NAME>TCCR4B</NAME>
<DESCRIPTION>Timer/Counter4 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A1</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC4</NAME>
<DESCRIPTION>Input Capture 4 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC4 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC4 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES4 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES4</NAME>
<DESCRIPTION>Input Capture 4 Edge Select</DESCRIPTION>
<TEXT>While the ICES4 bit is cleared (zero), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the falling edge of the input capture pin - ICP. While the ICES4 bit is set (one), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>WGM43</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM42</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS42</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 4</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T4, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS41</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 4</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T4, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS40</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 4</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR4B>
<TCCR4C>
<NAME>TCCR4C</NAME>
<DESCRIPTION>Timer/Counter 4 Control Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A2</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC4A</NAME>
<DESCRIPTION>Force Output Compare 4A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM4A1 and COM4A0.If the COM4A1 and COM4A0 bits are written in the same cycle as FOC4A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4A1 and COM4A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC4 in TCCR4B is set. The corresponding I/O pin must be set as an output pin for the FOC4A bit to have effect on the pin. The FOC4A bit will always be read as zero. The setting of the FOC4A bit has no effect in PWM m</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC4B</NAME>
<DESCRIPTION>Force Output Compare 4B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM4B1 and COM4B0.If the COM4B1 and COM4B0 bits are written in the same cycle as FOC4B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4B1 and COM4B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC4B bit to have effect on the pin. The FOC4B bit will always be read as zero. The setting of the FOC4B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>FOC4C</NAME>
<DESCRIPTION>Force Output Compare 4C</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM4B1 and COM4B0.If the COM4B1 and COM4B0 bits are written in the same cycle as FOC4B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4B1 and COM4B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC4B bit to have effect on the pin. The FOC4B bit will always be read as zero. The setting of the FOC4B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</TCCR4C>
<TCNT4H>
<NAME>TCNT4H</NAME>
<DESCRIPTION>Timer/Counter4 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter4. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR4A, OCR4B and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A5</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT4H7</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT4H6</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT4H5</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT4H4</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT4H3</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT4H2</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT4H1</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT4H0</NAME>
<DESCRIPTION>Timer/Counter4 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT4H>
<TCNT4L>
<NAME>TCNT4L</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter4. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR4A, OCR4B and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A4</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT4L7</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT4L6</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT4L5</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT4L4</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT4L3</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT4L2</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT4L1</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT4L0</NAME>
<DESCRIPTION>Timer/Counter4 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT4L>
<OCR4AH>
<NAME>OCR4AH</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register A High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interr</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A9</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4AH7</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4AH6</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4AH5</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4AH4</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4AH3</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4AH2</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4AH1</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4AH0</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4AH>
<OCR4AL>
<NAME>OCR4AL</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register A Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A8</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4AL7</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4AL6</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4AL5</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4AL4</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4AL3</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4AL2</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4AL1</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4AL0</NAME>
<DESCRIPTION>Timer/Counter4 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4AL>
<OCR4BH>
<NAME>OCR4BH</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AB</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4BH7</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4BH6</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4BH5</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4BH4</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4BH3</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4BH2</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4BH1</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4BH0</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4BH>
<OCR4BL>
<NAME>OCR4BL</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AA</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4BL7</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4BL6</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4BL5</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4BL4</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4BL3</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4BL2</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4BL1</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4BL0</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4BL>
<OCR4CH>
<NAME>OCR4CH</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AD</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4CH7</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4CH6</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4CH5</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4CH4</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4CH3</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4CH2</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4CH1</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4CH0</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4CH>
<OCR4CL>
<NAME>OCR4CL</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$AC</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR4CL7</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR4CL6</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR4CL5</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR4CL4</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR4CL3</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR4CL2</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR4CL1</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR4CL0</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR4CL>
<ICR4H>
<NAME>ICR4H</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES4) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter4 is transferred to the Input Capture Register - ICR4. At the same time, the input capture flag - ICF4 - is set (one). Since the Input Capture Register - ICR4 - is a 16-bit register, a temporary register TEMP is used when ICR4 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR4L, the data is sent to the CPU and the data of the high byte ICR4H is placed in the TEMP register. When the CPU reads the data in the high byte ICR4H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR4L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT4, OCR4A and OCR4B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A7</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR4H7</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR4H6</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR4H5</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR4H4</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR4H3</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR4H2</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR4H1</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR4H0</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR4H>
<ICR4L>
<NAME>ICR4L</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES4) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter4 is transferred to the Input Capture Register - ICR4. At the same time, the input capture flag - ICF4 - is set (one). Since the Input Capture Register - ICR4 - is a 16-bit register, a temporary register TEMP is used when ICR4 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR4L, the data is sent to the CPU and the data of the high byte ICR4H is placed in the TEMP register. When the CPU reads the data in the high byte ICR4H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR4L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT4, OCR4A and OCR4B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$A6</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR4L7</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR4L6</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR4L5</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR4L4</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR4L3</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR4L2</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR4L1</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR4L0</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR4L>
<TIMSK4>
<NAME>TIMSK4</NAME>
<DESCRIPTION>Timer/Counter4 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$72</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICIE4</NAME>
<DESCRIPTION>Timer/Counter4 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCIE4C</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare C Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE4C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCIE4B</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare B Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE4A</NAME>
<DESCRIPTION>Timer/Counter4 Output Compare A Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE4A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter4 occurs, i.e., when the OCF4A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE4</NAME>
<DESCRIPTION>Timer/Counter4 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter4 occurs, i.e., when the TOV4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK4>
<TIFR4>
<NAME>TIFR4</NAME>
<DESCRIPTION>Timer/Counter4 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$19</IO_ADDR>
<MEM_ADDR>$39</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF4</NAME>
<DESCRIPTION>Input Capture Flag 4</DESCRIPTION>
<TEXT>The ICF4 bit is set (one) to flag an input capture event, indicating that the Timer/Counter4 value has been transferred to the input capture register - ICR4. ICF4 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF4 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE4 (Timer/Counter4 Input Capture Interrupt Enable), and ICF4 are set (one), the Timer/Counter4 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCF4C</NAME>
<DESCRIPTION>Output Compare Flag 4C</DESCRIPTION>
<TEXT>The OCF4C bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCF4B</NAME>
<DESCRIPTION>Output Compare Flag 4B</DESCRIPTION>
<TEXT>The OCF4B bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF4A</NAME>
<DESCRIPTION>Output Compare Flag 4A</DESCRIPTION>
<TEXT>The OCF4A bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4A - Output Compare Register 4A. OCF4A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4A (Timer/Counter4 Compare match InterruptA Enable), and the OCF4A are set (one), the Timer/Counter4 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV4</NAME>
<DESCRIPTION>Timer/Counter4 Overflow Flag</DESCRIPTION>
<TEXT>The TOV4 is set (one) when an overflow occurs in Timer/Counter4. TOV4 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV4 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE4 (Timer/Counter4 Overflow Interrupt Enable), and TOV4 are set (one), the Timer/Counter4 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter4 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR4>
</TIMER_COUNTER_4>
<TIMER_COUNTER_3>
<LIST>[TIMSK3:TIFR3:TCCR3A:TCCR3B:TCCR3C:TCNT3H:TCNT3L:OCR3AH:OCR3AL:OCR3BH:OCR3BL:ICR3H:ICR3L:OCR3CH:OCR3CL]</LIST>
<LINK>[TCNT3H:TCNT3L];[OCR3AH:OCR3AL];[OCR3BH:OCR3BL];[OCR3CH:OCR3CL];[ICR3H:ICR3L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm3_03.xml</ID>
<TEXT/>
<TCCR3A>
<NAME>TCCR3A</NAME>
<DESCRIPTION>Timer/Counter3 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$90</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM3A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM3A0</NAME>
<DESCRIPTION>Compare Output Mode 3A, bit 0</DESCRIPTION>
<TEXT>The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM3B1</NAME>
<DESCRIPTION>Compare Output Mode 3B, bit 1</DESCRIPTION>
<TEXT>The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM3B0</NAME>
<DESCRIPTION>Compare Output Mode 3B, bit 0</DESCRIPTION>
<TEXT>The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>COM3C1</NAME>
<DESCRIPTION>Compare Output Mode 3C, bit 1</DESCRIPTION>
<TEXT>The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>COM3C0</NAME>
<DESCRIPTION>Compare Output Mode 3C, bit 0</DESCRIPTION>
<TEXT>The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WGM31</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM30</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR3A>
<TCCR3B>
<NAME>TCCR3B</NAME>
<DESCRIPTION>Timer/Counter3 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$91</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC3</NAME>
<DESCRIPTION>Input Capture 3 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES3</NAME>
<DESCRIPTION>Input Capture 3 Edge Select</DESCRIPTION>
<TEXT>While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>WGM33</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM32</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS32</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 3</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS31</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 3</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS30</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 3</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR3B>
<TCCR3C>
<NAME>TCCR3C</NAME>
<DESCRIPTION>Timer/Counter 3 Control Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$92</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC3A</NAME>
<DESCRIPTION>Force Output Compare 3A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM3A1 and COM3A0.If the COM3A1 and COM3A0 bits are written in the same cycle as FOC3A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3A1 and COM3A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC3 in TCCR3B is set. The corresponding I/O pin must be set as an output pin for the FOC3A bit to have effect on the pin. The FOC3A bit will always be read as zero. The setting of the FOC3A bit has no effect in PWM m</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC3B</NAME>
<DESCRIPTION>Force Output Compare 3B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>FOC3C</NAME>
<DESCRIPTION>Force Output Compare 3C</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</TCCR3C>
<TCNT3H>
<NAME>TCNT3H</NAME>
<DESCRIPTION>Timer/Counter3 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR3A, OCR3B and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$95</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT3H7</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT3H6</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT3H5</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT3H4</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT3H3</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT3H2</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT3H1</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT3H0</NAME>
<DESCRIPTION>Timer/Counter3 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT3H>
<TCNT3L>
<NAME>TCNT3L</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR3A, OCR3B and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$94</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT3L7</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT3L6</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT3L5</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT3L4</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT3L3</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT3L2</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT3L1</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT3L0</NAME>
<DESCRIPTION>Timer/Counter3 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT3L>
<OCR3AH>
<NAME>OCR3AH</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register A High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interr</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$99</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3AH7</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3AH6</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3AH5</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3AH4</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3AH3</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3AH2</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3AH1</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3AH0</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3AH>
<OCR3AL>
<NAME>OCR3AL</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register A Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$98</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3AL7</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3AL6</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3AL5</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3AL4</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3AL3</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3AL2</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3AL1</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3AL0</NAME>
<DESCRIPTION>Timer/Counter3 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3AL>
<OCR3BH>
<NAME>OCR3BH</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3BH7</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3BH6</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3BH5</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3BH4</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3BH3</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3BH2</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3BH1</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3BH0</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3BH>
<OCR3BL>
<NAME>OCR3BL</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3BL7</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3BL6</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3BL5</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3BL4</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3BL3</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3BL2</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3BL1</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3BL0</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3BL>
<OCR3CH>
<NAME>OCR3CH</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3CH7</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3CH6</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3CH5</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3CH4</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3CH3</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3CH2</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3CH1</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3CH0</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3CH>
<OCR3CL>
<NAME>OCR3CL</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$9C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR3CL7</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR3CL6</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR3CL5</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR3CL4</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR3CL3</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR3CL2</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR3CL1</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR3CL0</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR3CL>
<ICR3H>
<NAME>ICR3H</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR3. At the same time, the input capture flag - ICF3 - is set (one). Since the Input Capture Register - ICR3 - is a 16-bit register, a temporary register TEMP is used when ICR3 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT3, OCR3A and OCR3B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$97</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR3H7</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR3H6</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR3H5</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR3H4</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR3H3</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR3H2</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR3H1</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR3H0</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR3H>
<ICR3L>
<NAME>ICR3L</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR3. At the same time, the input capture flag - ICF3 - is set (one). Since the Input Capture Register - ICR3 - is a 16-bit register, a temporary register TEMP is used when ICR3 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT3, OCR3A and OCR3B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$96</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR3L7</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR3L6</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR3L5</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR3L4</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR3L3</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR3L2</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR3L1</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR3L0</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR3L>
<TIMSK3>
<NAME>TIMSK3</NAME>
<DESCRIPTION>Timer/Counter3 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$71</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICIE3</NAME>
<DESCRIPTION>Timer/Counter3 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCIE3C</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare C Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE3C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCIE3B</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare B Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE3B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE3A</NAME>
<DESCRIPTION>Timer/Counter3 Output Compare A Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE3A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE3</NAME>
<DESCRIPTION>Timer/Counter3 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK3>
<TIFR3>
<NAME>TIFR3</NAME>
<DESCRIPTION>Timer/Counter3 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$18</IO_ADDR>
<MEM_ADDR>$38</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF3</NAME>
<DESCRIPTION>Input Capture Flag 3</DESCRIPTION>
<TEXT>The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR3. ICF3 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCF3C</NAME>
<DESCRIPTION>Output Compare Flag 3C</DESCRIPTION>
<TEXT>The OCF3C bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCF3B</NAME>
<DESCRIPTION>Output Compare Flag 3B</DESCRIPTION>
<TEXT>The OCF3B bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF3A</NAME>
<DESCRIPTION>Output Compare Flag 3A</DESCRIPTION>
<TEXT>The OCF3A bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3A - Output Compare Register 3A. OCF3A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3A are set (one), the Timer/Counter3 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV3</NAME>
<DESCRIPTION>Timer/Counter3 Overflow Flag</DESCRIPTION>
<TEXT>The TOV3 is set (one) when an overflow occurs in Timer/Counter3. TOV3 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE3 (Timer/Counter3 Overflow Interrupt Enable), and TOV3 are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR3>
</TIMER_COUNTER_3>
<TIMER_COUNTER_1>
<LIST>[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:OCR1CH:OCR1CL]</LIST>
<LINK>[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[OCR1CH:OCR1CL];[ICR1H:ICR1L]</LINK>
<ICON>io_timer.bmp</ICON>
<ID>t16pwm1_14.xml</ID>
<TEXT/>
<TCCR1A>
<NAME>TCCR1A</NAME>
<DESCRIPTION>Timer/Counter1 Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$80</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>COM1A1</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 1</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>COM1A0</NAME>
<DESCRIPTION>Compare Output Mode 1A, bit 0</DESCRIPTION>
<TEXT>The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>COM1B1</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 1</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>COM1B0</NAME>
<DESCRIPTION>Compare Output Mode 1B, bit 0</DESCRIPTION>
<TEXT>The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>COM1C1</NAME>
<DESCRIPTION>Compare Output Mode 1C, bit 1</DESCRIPTION>
<TEXT>The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>COM1C0</NAME>
<DESCRIPTION>Compare Output Mode 1C, bit 0</DESCRIPTION>
<TEXT>The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>WGM11</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>WGM10</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1A>
<TCCR1B>
<NAME>TCCR1B</NAME>
<DESCRIPTION>Timer/Counter1 Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$81</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ICNC1</NAME>
<DESCRIPTION>Input Capture 1 Noise Canceler</DESCRIPTION>
<TEXT>When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICES1</NAME>
<DESCRIPTION>Input Capture 1 Edge Select</DESCRIPTION>
<TEXT>While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT4>
<NAME>WGM13</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WGM12</NAME>
<DESCRIPTION>Waveform Generation Mode</DESCRIPTION>
<TEXT>Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CS12</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CS11</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CS10</NAME>
<DESCRIPTION>Prescaler source of Timer/Counter 1</DESCRIPTION>
<TEXT>Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCCR1B>
<TCCR1C>
<NAME>TCCR1C</NAME>
<DESCRIPTION>Timer/Counter 1 Control Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$82</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>FOC1A</NAME>
<DESCRIPTION>Force Output Compare 1A</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM m</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>FOC1B</NAME>
<DESCRIPTION>Force Output Compare 1B</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>FOC1C</NAME>
<DESCRIPTION>Force Output Compare 1C</DESCRIPTION>
<TEXT>Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
</TCCR1C>
<TCNT1H>
<NAME>TCNT1H</NAME>
<DESCRIPTION>Timer/Counter1 High Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$85</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1H7</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1H6</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1H5</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1H4</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1H3</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1H2</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1H1</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1H0</NAME>
<DESCRIPTION>Timer/Counter1 High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1H>
<TCNT1L>
<NAME>TCNT1L</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte</DESCRIPTION>
<TEXT>This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$84</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>TCNT1L7</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TCNT1L6</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>TCNT1L5</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>TCNT1L4</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TCNT1L3</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>TCNT1L2</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>TCNT1L1</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TCNT1L0</NAME>
<DESCRIPTION>Timer/Counter1 Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TCNT1L>
<OCR1AH>
<NAME>OCR1AH</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register A High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interr</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$89</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AH7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AH6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AH5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AH4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AH3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AH2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AH1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AH0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AH>
<OCR1AL>
<NAME>OCR1AL</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register A Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$88</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1AL7</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1AL6</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1AL5</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1AL4</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1AL3</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1AL2</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1AL1</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1AL0</NAME>
<DESCRIPTION>Timer/Counter1 Outbut Compare Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1AL>
<OCR1BH>
<NAME>OCR1BH</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8B</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BH7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BH6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BH5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BH4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BH3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BH2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BH1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BH0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BH>
<OCR1BL>
<NAME>OCR1BL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8A</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1BL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1BL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1BL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1BL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1BL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1BL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1BL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1BL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1BL>
<OCR1CH>
<NAME>OCR1CH</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register B High Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8D</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1CH7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1CH6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1CH5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1CH4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1CH3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1CH2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1CH1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1CH0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1CH>
<OCR1CL>
<NAME>OCR1CL</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register B Low Byte</DESCRIPTION>
<TEXT>The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$8C</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCR1CL7</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCR1CL6</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCR1CL5</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCR1CL4</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCR1CL3</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCR1CL2</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCR1CL1</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCR1CL0</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCR1CL>
<ICR1H>
<NAME>ICR1H</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$87</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1H7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1H6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1H5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1H4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1H3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1H2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1H1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1H0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register High Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1H>
<ICR1L>
<NAME>ICR1L</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte</DESCRIPTION>
<TEXT>The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$86</MEM_ADDR>
<ICON>io_timer.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ICR1L7</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ICR1L6</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ICR1L5</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ICR1L4</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ICR1L3</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ICR1L2</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ICR1L1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ICR1L0</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Register Low Byte bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ICR1L>
<TIMSK1>
<NAME>TIMSK1</NAME>
<DESCRIPTION>Timer/Counter1 Interrupt Mask Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6F</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICIE1</NAME>
<DESCRIPTION>Timer/Counter1 Input Capture Interrupt Enable</DESCRIPTION>
<TEXT>When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCIE1C</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare C Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCIE1B</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare B Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCIE1A</NAME>
<DESCRIPTION>Timer/Counter1 Output Compare A Match Interrupt Enable</DESCRIPTION>
<TEXT>When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOIE1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Interrupt Enable</DESCRIPTION>
<TEXT>When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIMSK1>
<TIFR1>
<NAME>TIFR1</NAME>
<DESCRIPTION>Timer/Counter1 Interrupt Flag register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$16</IO_ADDR>
<MEM_ADDR>$36</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>ICF1</NAME>
<DESCRIPTION>Input Capture Flag 1</DESCRIPTION>
<TEXT>The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>OCF1C</NAME>
<DESCRIPTION>Output Compare Flag 1C</DESCRIPTION>
<TEXT>The OCF1C bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCF1B</NAME>
<DESCRIPTION>Output Compare Flag 1B</DESCRIPTION>
<TEXT>The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCF1A</NAME>
<DESCRIPTION>Output Compare Flag 1A</DESCRIPTION>
<TEXT>The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TOV1</NAME>
<DESCRIPTION>Timer/Counter1 Overflow Flag</DESCRIPTION>
<TEXT>The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</TIFR1>
</TIMER_COUNTER_1>
<JTAG>
<LIST>[OCDR:MCUCR:MCUSR]</LIST>
<LINK/>
<RULES/>
<ICON>io_com.bmp</ICON>
<ID>00</ID>
<TEXT>JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – The Internal Register File –Program Counter – EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: –AVR Break Instruction – Break on Change of Program Memory Flow –Single Step Break –Program Memory Breakpoints on Single Address or Address Range – Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR Stu</TEXT>
<OCDR>
<NAME>OCDR</NAME>
<DESCRIPTION>On-Chip Debug Related Register in I/O Memory</DESCRIPTION>
<TEXT>The OCDR register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Reg-ister Dirty - IDRD - is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR reg-ister the 7 LSB will be from the OCDR register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this registe</TEXT>
<IO_ADDR>$31</IO_ADDR>
<MEM_ADDR>$51</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>OCDR7</NAME>
<ALIAS>IDRD</ALIAS>
<DESCRIPTION>On-Chip Debug Register Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>OCDR6</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>OCDR5</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>OCDR4</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>OCDR3</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>OCDR2</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>OCDR1</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>OCDR0</NAME>
<DESCRIPTION>On-Chip Debug Register Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OCDR>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>JTD</NAME>
<DESCRIPTION>JTAG Interface Disable</DESCRIPTION>
<TEXT>When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>JTRF</NAME>
<DESCRIPTION>JTAG Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.This bit is reset by a Power-on reset,or by writing a logic zero to the flag. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
</MCUSR>
</JTAG>
<EXTERNAL_INTERRUPT>
<LIST>[EICRA:EICRB:EIMSK:EIFR:PCICR:PCIFR:PCMSK2:PCMSK1:PCMSK0]</LIST>
<LINK>[PCMSK2:PCMSK1:PCMSK0]</LINK>
<ICON>io_ext.bmp</ICON>
<ID/>
<TEXT>The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt</TEXT>
<EICRA>
<NAME>EICRA</NAME>
<DESCRIPTION>External Interrupt Control Register A</DESCRIPTION>
<TEXT>This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enable</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$69</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ISC31</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ISC30</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ISC21</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ISC20</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC11</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC10</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC01</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC00</NAME>
<DESCRIPTION>External Interrupt Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EICRA>
<EICRB>
<NAME>EICRB</NAME>
<DESCRIPTION>External Interrupt Control Register B</DESCRIPTION>
<TEXT>The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 49. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ISC71</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ISC70</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ISC61</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ISC60</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ISC51</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ISC50</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ISC41</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ISC40</NAME>
<DESCRIPTION>External Interrupt 7-4 Sense Control Bit</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EICRB>
<EIMSK>
<NAME>EIMSK</NAME>
<DESCRIPTION>External Interrupt Mask Register</DESCRIPTION>
<TEXT>When an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. </TEXT>
<IO_ADDR>$1D</IO_ADDR>
<MEM_ADDR>$3D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INT7</NAME>
<DESCRIPTION>External Interrupt Request 7 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INT6</NAME>
<DESCRIPTION>External Interrupt Request 6 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>INT5</NAME>
<DESCRIPTION>External Interrupt Request 5 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>INT4</NAME>
<DESCRIPTION>External Interrupt Request 4 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>INT3</NAME>
<DESCRIPTION>External Interrupt Request 3 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>INT2</NAME>
<DESCRIPTION>External Interrupt Request 2 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INT1</NAME>
<DESCRIPTION>External Interrupt Request 1 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INT0</NAME>
<DESCRIPTION>External Interrupt Request 0 Enable</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIMSK>
<EIFR>
<NAME>EIFR</NAME>
<DESCRIPTION>External Interrupt Flag Register</DESCRIPTION>
<TEXT>When an event on the INT7 - INT0 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical one to it. Note that when entering some sleep modes with the INT3:0 interrupts disabled, the input buffers on these pin will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 54 for more informa</TEXT>
<IO_ADDR>$1C</IO_ADDR>
<MEM_ADDR>$3C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>INTF7</NAME>
<DESCRIPTION>External Interrupt Flag 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>INTF6</NAME>
<DESCRIPTION>External Interrupt Flag 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>INTF5</NAME>
<DESCRIPTION>External Interrupt Flag 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>INTF4</NAME>
<DESCRIPTION>External Interrupt Flag 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>INTF3</NAME>
<DESCRIPTION>External Interrupt Flag 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>INTF2</NAME>
<DESCRIPTION>External Interrupt Flag 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>INTF1</NAME>
<DESCRIPTION>External Interrupt Flag 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>INTF0</NAME>
<DESCRIPTION>External Interrupt Flag 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIFR>
<PCMSK2>
<NAME>PCMSK2</NAME>
<DESCRIPTION>Pin Change Mask Register 2</DESCRIPTION>
<TEXT>Each PCINT23..16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6D</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT23</NAME>
<DESCRIPTION>Pin Change Enable Mask 23</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT22</NAME>
<DESCRIPTION>Pin Change Enable Mask 22</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT21</NAME>
<DESCRIPTION>Pin Change Enable Mask 21</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT20</NAME>
<DESCRIPTION>Pin Change Enable Mask 20</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT19</NAME>
<DESCRIPTION>Pin Change Enable Mask 19</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT18</NAME>
<DESCRIPTION>Pin Change Enable Mask 18</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT17</NAME>
<DESCRIPTION>Pin Change Enable Mask 17</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT16</NAME>
<DESCRIPTION>Pin Change Enable Mask 16</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK2>
<PCMSK1>
<NAME>PCMSK1</NAME>
<DESCRIPTION>Pin Change Mask Register 1</DESCRIPTION>
<TEXT>Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$6C</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT15</NAME>
<DESCRIPTION>Pin Change Enable Mask 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT14</NAME>
<DESCRIPTION>Pin Change Enable Mask 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT13</NAME>
<DESCRIPTION>Pin Change Enable Mask 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT12</NAME>
<DESCRIPTION>Pin Change Enable Mask 12</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT11</NAME>
<DESCRIPTION>Pin Change Enable Mask 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT10</NAME>
<DESCRIPTION>Pin Change Enable Mask 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT9</NAME>
<DESCRIPTION>Pin Change Enable Mask 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT8</NAME>
<DESCRIPTION>Pin Change Enable Mask 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK1>
<PCMSK0>
<NAME>PCMSK0</NAME>
<DESCRIPTION>Pin Change Mask Register 0</DESCRIPTION>
<TEXT>Each PCINT bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>0x6B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>PCINT7</NAME>
<DESCRIPTION>Pin Change Enable Mask 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PCINT6</NAME>
<DESCRIPTION>Pin Change Enable Mask 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PCINT5</NAME>
<DESCRIPTION>Pin Change Enable Mask 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PCINT4</NAME>
<DESCRIPTION>Pin Change Enable Mask 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PCINT3</NAME>
<DESCRIPTION>Pin Change Enable Mask 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PCINT2</NAME>
<DESCRIPTION>Pin Change Enable Mask 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCINT1</NAME>
<DESCRIPTION>Pin Change Enable Mask 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCINT0</NAME>
<DESCRIPTION>Pin Change Enable Mask 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCMSK0>
<PCIFR>
<NAME>PCIFR</NAME>
<DESCRIPTION>Pin Change Interrupt Flag Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$1B</IO_ADDR>
<MEM_ADDR>$3B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>PCIF2</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 2</DESCRIPTION>
<TEXT>When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCIF1</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 1</DESCRIPTION>
<TEXT>When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCIF0</NAME>
<DESCRIPTION>Pin Change Interrupt Flag 0</DESCRIPTION>
<TEXT>When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCIFR>
<PCICR>
<NAME>PCICR</NAME>
<DESCRIPTION>Pin Change Interrupt Control Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$68</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT2>
<NAME>PCIE2</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 2</DESCRIPTION>
<TEXT></TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PCIE1</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 1</DESCRIPTION>
<TEXT></TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PCIE0</NAME>
<DESCRIPTION>Pin Change Interrupt Enable 0</DESCRIPTION>
<TEXT></TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PCICR>
</EXTERNAL_INTERRUPT>
<CPU>
<LIST>[SREG:SPH:SPL:MCUCR:MCUSR:XMCRA:XMCRB:OSCCAL:CLKPR:SMCR:RAMPZ:EIND:GPIOR2:GPIOR1:GPIOR0:PRR1:PRR0]</LIST>
<LINK>[SPH:SPL]</LINK>
<ICON>io_cpu.bmp</ICON>
<ID/>
<TEXT/>
<SREG>
<NAME>SREG</NAME>
<DESCRIPTION>Status Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3F</IO_ADDR>
<MEM_ADDR>$5F</MEM_ADDR>
<ICON>io_sreg.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>I</NAME>
<DESCRIPTION>Global Interrupt Enable</DESCRIPTION>
<TEXT>The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>T</NAME>
<DESCRIPTION>Bit Copy Storage</DESCRIPTION>
<TEXT>The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>H</NAME>
<DESCRIPTION>Half Carry Flag</DESCRIPTION>
<TEXT>The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>S</NAME>
<DECRIPTION>Sign Bit</DECRIPTION>
<TEXT>The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>V</NAME>
<DESCRIPTION>Two's Complement Overflow Flag</DESCRIPTION>
<TEXT>The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>N</NAME>
<DESCRIPTION>Negative Flag</DESCRIPTION>
<TEXT>The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>Z</NAME>
<DESCRIPTION>Zero Flag</DESCRIPTION>
<TEXT>The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>C</NAME>
<DESCRIPTION>Carry Flag</DESCRIPTION>
<TEXT>The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SREG>
<SPH>
<NAME>SPH</NAME>
<DESCRIPTION>Stack Pointer High</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R</TEXT>
<IO_ADDR>$3E</IO_ADDR>
<MEM_ADDR>$5E</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP15</NAME>
<DESCRIPTION>Stack pointer bit 15</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP14</NAME>
<DESCRIPTION>Stack pointer bit 14</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP13</NAME>
<DESCRIPTION>Stack pointer bit 13</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP12</NAME>
<DECRIPTION>Stack pointer bit 12</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP11</NAME>
<DESCRIPTION>Stack pointer bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP10</NAME>
<DESCRIPTION>Stack pointer bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP9</NAME>
<DESCRIPTION>Stack pointer bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP8</NAME>
<DESCRIPTION>Stack pointer bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</SPH>
<SPL>
<NAME>SPL</NAME>
<DESCRIPTION>Stack Pointer Low</DESCRIPTION>
<TEXT>The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt </TEXT>
<IO_ADDR>$3D</IO_ADDR>
<MEM_ADDR>$5D</MEM_ADDR>
<ICON>io_sph.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>SP7</NAME>
<DESCRIPTION>Stack pointer bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SP6</NAME>
<DESCRIPTION>Stack pointer bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SP5</NAME>
<DESCRIPTION>Stack pointer bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SP4</NAME>
<DECRIPTION>Stack pointer bit 4</DECRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SP3</NAME>
<DESCRIPTION>Stack pointer bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SP2</NAME>
<DESCRIPTION>Stack pointer bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SP1</NAME>
<DESCRIPTION>Stack pointer bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SP0</NAME>
<DESCRIPTION>Stack pointer bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT0>
</SPL>
<MCUCR>
<NAME>MCUCR</NAME>
<DESCRIPTION>MCU Control Register</DESCRIPTION>
<TEXT>The MCU Control Register contains control bits for general MCU functions.</TEXT>
<IO_ADDR>$35</IO_ADDR>
<MEM_ADDR>$55</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>JTD</NAME>
<DESCRIPTION>JTAG Interface Disable</DESCRIPTION>
<TEXT>When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT4>
<NAME>PUD</NAME>
<DESCRIPTION>Pull-up disable</DESCRIPTION>
<TEXT>When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT1>
<NAME>IVSEL</NAME>
<DESCRIPTION>Interrupt Vector Select</DESCRIPTION>
<TEXT>When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>IVCE</NAME>
<DESCRIPTION>Interrupt Vector Change Enable</DESCRIPTION>
<TEXT>The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUCR>
<MCUSR>
<NAME>MCUSR</NAME>
<DESCRIPTION>MCU Status Register</DESCRIPTION>
<TEXT>The MCU Status Register provides information on which reset source caused an MCU reset.</TEXT>
<IO_ADDR>$34</IO_ADDR>
<MEM_ADDR>$54</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT4>
<NAME>JTRF</NAME>
<DESCRIPTION>JTAG Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Flag</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>WDRF</NAME>
<DESCRIPTION>Watchdog Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>BORF</NAME>
<DESCRIPTION>Brown-out Reset Flag</DESCRIPTION>
<TEXT>This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>EXTRF</NAME>
<DESCRIPTION>External Reset Flag</DESCRIPTION>
<TEXT>This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PORF</NAME>
<DESCRIPTION>Power-on reset flag</DESCRIPTION>
<TEXT>This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.</TEXT>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</MCUSR>
<XMCRA>
<NAME>XMCRA</NAME>
<DESCRIPTION>External Memory Control Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$74</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SRE</NAME>
<DESCRIPTION>External SRAM Enable</DESCRIPTION>
<TEXT>Writing SRE to one enables the External Memory Interface.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>SRL2</NAME>
<DESCRIPTION>Wait state page limit</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SRL1</NAME>
<DESCRIPTION>Wait state page limit</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>SRL0</NAME>
<DESCRIPTION>Wait state page limit</DESCRIPTION>
<TEXT>It is possible to configure different wait-states for different external memory addresses.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>SRW11</NAME>
<DESCRIPTION>Wait state select bit upper page</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SRW10</NAME>
<DESCRIPTION>Wait state select bit upper page</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SRW01</NAME>
<DESCRIPTION>Wait state select bit lower page</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SRW00</NAME>
<DESCRIPTION>Wait state select bit lower page</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</XMCRA>
<XMCRB>
<NAME>XMCRB</NAME>
<DESCRIPTION>External Memory Control Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$75</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>XMBK</NAME>
<DESCRIPTION>External Memory Bus Keeper Enable</DESCRIPTION>
<TEXT>Port C pins release command.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT2>
<NAME>XMM2</NAME>
<DESCRIPTION>External Memory High Mask</DESCRIPTION>
<TEXT>Port C pins released.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>XMM1</NAME>
<DESCRIPTION>External Memory High Mask</DESCRIPTION>
<TEXT>Port C pins released.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>XMM0</NAME>
<DESCRIPTION>External Memory High Mask</DESCRIPTION>
<TEXT>Port C pins released.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</XMCRB>
<OSCCAL>
<NAME>OSCCAL</NAME>
<DESCRIPTION>Oscillator Calibration Value</DESCRIPTION>
<TEXT>Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$66</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>CAL7</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit7</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>CAL6</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit6</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>CAL5</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>CAL4</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>CAL3</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>CAL2</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>CAL1</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>CAL0</NAME>
<DESCRIPTION>Oscillator Calibration Value Bit0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</OSCCAL>
<CLKPR>
<NAME>CLKPR</NAME>
<DESCRIPTION/>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$61</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>CLKPCE</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT7>
<BIT3>
<NAME>CLKPS3</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT3>
<BIT2>
<NAME>CLKPS2</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT2>
<BIT1>
<NAME>CLKPS1</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT1>
<BIT0>
<NAME>CLKPS0</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS/>
<INIT_VAL/>
</BIT0>
</CLKPR>
<SMCR>
<NAME>SMCR</NAME>
<DESCRIPTION>Sleep Mode Control Register</DESCRIPTION>
<TEXT>The Sleep Mode Control Register contains control bits for power management.</TEXT>
<IO_ADDR>$33</IO_ADDR>
<MEM_ADDR>$53</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT3>
<NAME>SM2</NAME>
<DESCRIPTION>Sleep Mode Select bit 2</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>SM1</NAME>
<DESCRIPTION>Sleep Mode Select bit 1</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>SM0</NAME>
<DESCRIPTION>Sleep Mode Select bit 0</DESCRIPTION>
<TEXT>These bits select between the five available sleep modes.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SE</NAME>
<DESCRIPTION>Sleep Enable</DESCRIPTION>
<TEXT>The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SMCR>
<EIND>
<NAME>EIND</NAME>
<DESCRIPTION>Extended Indirect Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3C</IO_ADDR>
<MEM_ADDR>$5C</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT0>
<NAME>EIND0</NAME>
<DESCRIPTION>Bit 0</DESCRIPTION>
<TEXT>For EICALL/EIJMP instructions.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</EIND>
<RAMPZ>
<NAME>RAMPZ</NAME>
<DESCRIPTION>RAM Page Z Select Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>$3B</IO_ADDR>
<MEM_ADDR>$5B</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT1>
<NAME>RAMPZ1</NAME>
<DESCRIPTION>RAM Page Z Select Register Bit 1</DESCRIPTION>
<TEXT>The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>RAMPZ0</NAME>
<DESCRIPTION>RAM Page Z Select Register Bit 0</DESCRIPTION>
<TEXT>The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</RAMPZ>
<GPIOR2>
<NAME>GPIOR2</NAME>
<DESCRIPTION>General Purpose IO Register 2</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>$2B</IO_ADDR>
<MEM_ADDR>$4B</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR27</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR26</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR25</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR24</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR23</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR22</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR21</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR20</NAME>
<DESCRIPTION>General Purpose IO Register 2 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR2>
<GPIOR1>
<NAME>GPIOR1</NAME>
<DESCRIPTION>General Purpose IO Register 1</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>$2A</IO_ADDR>
<MEM_ADDR>$4A</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR17</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR16</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR15</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR14</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR13</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR12</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR11</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR10</NAME>
<DESCRIPTION>General Purpose IO Register 1 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR1>
<GPIOR0>
<NAME>GPIOR0</NAME>
<DESCRIPTION>General Purpose IO Register 0</DESCRIPTION>
<TEXT>The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. </TEXT>
<IO_ADDR>$1E</IO_ADDR>
<MEM_ADDR>$3E</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>GPIOR07</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>GPIOR06</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>GPIOR05</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>GPIOR04</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>GPIOR03</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>GPIOR02</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>GPIOR01</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>GPIOR00</NAME>
<DESCRIPTION>General Purpose IO Register 0 bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</GPIOR0>
<PRR1>
<NAME>PRR1</NAME>
<DESCRIPTION>Power Reduction Register1</DESCRIPTION>
<TEXT>The Power Reduction Register, PRR1, provides a method to stop the clock to individual peripherals to reduce power consumption.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$65</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT5>
<NAME>PRTIM5</NAME>
<DESCRIPTION>Power Reduction Timer/Counter5</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>PRTIM4</NAME>
<DESCRIPTION>Power Reduction Timer/Counter4</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>PRTIM3</NAME>
<DESCRIPTION>Power Reduction Timer/Counter3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRUSART3</NAME>
<DESCRIPTION>Power Reduction USART3</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRUSART2</NAME>
<DESCRIPTION>Power Reduction USART2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRUSART1</NAME>
<DESCRIPTION>Power Reduction USART1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PRR1>
<PRR0>
<NAME>PRR0</NAME>
<DESCRIPTION>Power Reduction Register0</DESCRIPTION>
<TEXT>The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$64</MEM_ADDR>
<ICON>io_cpu.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>PRTWI</NAME>
<DESCRIPTION>Power Reduction TWI</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>PRTIM2</NAME>
<DESCRIPTION>Power Reduction Timer/Counter2</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>PRTIM0</NAME>
<DESCRIPTION>Power Reduction Timer/Counter0</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT3>
<NAME>PRTIM1</NAME>
<DESCRIPTION>Power Reduction Timer/Counter1</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PRSPI</NAME>
<DESCRIPTION>Power Reduction Serial Peripheral Interface</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PRUSART0</NAME>
<DESCRIPTION>Power Reduction USART</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>PRADC</NAME>
<DESCRIPTION>Power Reduction ADC</DESCRIPTION>
<TEXT/>
<ACCESS>R/W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</PRR0>
</CPU>
<AD_CONVERTER>
<LIST>[ADMUX:ADCSRA:ADCSRB:ADCH:ADCL:DIDR0:DIDR2]</LIST>
<LINK/>
<RULES>((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);</RULES>
<ICON>io_analo.bmp</ICON>
<ID/>
<TEXT>AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode No</TEXT>
<ADMUX>
<NAME>ADMUX</NAME>
<DESCRIPTION>The ADC multiplexer Selection Register</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7C</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>REFS1</NAME>
<DESCRIPTION>Reference Selection Bit 1</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>REFS0</NAME>
<DESCRIPTION>Reference Selection Bit 0</DESCRIPTION>
<TEXT>These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADLAR</NAME>
<DESCRIPTION>Left Adjust Result</DESCRIPTION>
<TEXT>The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. </TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>MUX4</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>MUX3</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>MUX2</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>MUX1</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MUX0</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADMUX>
<ADCH>
<NAME>ADCH</NAME>
<DESCRIPTION>ADC Data Register High Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$79</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCH7</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCH6</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCH5</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCH4</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCH3</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCH2</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCH1</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCH0</NAME>
<DESCRIPTION>ADC Data Register High Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCH>
<ADCL>
<NAME>ADCL</NAME>
<DESCRIPTION>ADC Data Register Low Byte</DESCRIPTION>
<TEXT>When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$78</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>ADCL7</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADCL6</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADCL5</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADCL4</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADCL3</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADCL2</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADCL1</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADCL0</NAME>
<DESCRIPTION>ADC Data Register Low Byte Bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCL>
<ADCSRA>
<NAME>ADCSRA</NAME>
<DESCRIPTION>The ADC Control and Status register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7A</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADEN</NAME>
<DESCRIPTION>ADC Enable</DESCRIPTION>
<TEXT>Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADSC</NAME>
<DESCRIPTION>ADC Start Conversion</DESCRIPTION>
<TEXT>In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADATE</NAME>
<DESCRIPTION>ADC Auto Trigger Enable</DESCRIPTION>
<TEXT>When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADIF</NAME>
<DESCRIPTION>ADC Interrupt Flag</DESCRIPTION>
<TEXT>This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADIE</NAME>
<DESCRIPTION>ADC Interrupt Enable</DESCRIPTION>
<TEXT>When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADPS2</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADPS1</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADPS0</NAME>
<DESCRIPTION>ADC Prescaler Select Bits</DESCRIPTION>
<TEXT>These bits determine the division factor between the XTAL frequency and the input clock to the ADC.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRA>
<ADCSRB>
<NAME>ADCSRB</NAME>
<DESCRIPTION>The ADC Control and Status register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7B</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT6>
<NAME>ACME</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT3>
<NAME>MUX5</NAME>
<DESCRIPTION>Analog Channel and Gain Selection Bits</DESCRIPTION>
<TEXT>The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADTS2</NAME>
<DESCRIPTION>ADC Auto Trigger Source bit 2</DESCRIPTION>
<TEXT>Please refer to table on page 240 in datasheet for trigger selection.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADTS1</NAME>
<DESCRIPTION>ADC Auto Trigger Source bit 1</DESCRIPTION>
<TEXT>Please refer to table on page 240 in datasheet for trigger selection.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADTS0</NAME>
<DESCRIPTION>ADC Auto Trigger Source bit 0</DESCRIPTION>
<TEXT>Please refer to table on page 240 in datasheet for trigger selection.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</ADCSRB>
<DIDR2>
<NAME>DIDR2</NAME>
<DESCRIPTION>Digital Input Disable Register</DESCRIPTION>
<TEXT>When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7D</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADC15D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADC14D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADC13D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADC12D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADC11D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADC10D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADC9D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADC8D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DIDR2>
<DIDR0>
<NAME>DIDR0</NAME>
<DESCRIPTION>Digital Input Disable Register</DESCRIPTION>
<TEXT>When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$7E</MEM_ADDR>
<ICON>io_analo.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>ADC7D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>ADC6D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>ADC5D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>ADC4D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>ADC3D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>ADC2D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>ADC1D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>ADC0D</NAME>
<DESCRIPTION/>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</DIDR0>
</AD_CONVERTER>
<BOOT_LOAD>
<LIST>[SPMCSR]</LIST>
<LINK/>
<RULES/>
<ICON>io_cpu.bmp</ICON>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<TEXT>The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor</TEXT>
<SPMCSR>
<NAME>SPMCSR</NAME>
<DESCRIPTION>Store Program Memory Control Register</DESCRIPTION>
<TEXT>The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.</TEXT>
<IO_ADDR>$37</IO_ADDR>
<MEM_ADDR>$57</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>SPMIE</NAME>
<DESCRIPTION>SPM Interrupt Enable</DESCRIPTION>
<TEXT>When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>RWWSB</NAME>
<DESCRIPTION>Read While Write Section Busy</DESCRIPTION>
<TEXT>When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>SIGRD</NAME>
<DESCRIPTION>Signature Row Read</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RWWSRE</NAME>
<DESCRIPTION>Read While Write section read enable</DESCRIPTION>
<TEXT>When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>BLBSET</NAME>
<DESCRIPTION>Boot Lock Bit Set</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>PGWRT</NAME>
<DESCRIPTION>Page Write</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>PGERS</NAME>
<DESCRIPTION>Page Erase</DESCRIPTION>
<TEXT>If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>SPMEN</NAME>
<DESCRIPTION>Store Program Memory Enable</DESCRIPTION>
<TEXT>This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</SPMCSR>
</BOOT_LOAD>
<USART2>
<LIST>[UDR2:UCSR2A:UCSR2B:UCSR2C:UBRR2H:UBRR2L]</LIST>
<LINK>[UBRR2H:UBRR2L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica</TEXT>
<UDR2>
<NAME>UDR2</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR2 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D6</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR2-7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR2-6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR2-5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR2-4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR2-3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR2-2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR2-1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR2-0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR2>
<UCSR2A>
<NAME>UCSR2A</NAME>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D0</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC2</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC2</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE2</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE2</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR2</NAME>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE2</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X2</NAME>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM2</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR2A>
<UCSR2B>
<NAME>UCSR2B</NAME>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D1</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE2</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE2</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE2</NAME>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN2</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN2</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ22</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB82</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB82</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR2B>
<UCSR2C>
<NAME>UCSR2C</NAME>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D2</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UMSEL21</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL20</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM21</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM20</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS2</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ21</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ20</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL2</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR2C>
<UBRR2H>
<NAME>UBRR2H</NAME>
<DESCRIPTION>USART Baud Rate Register High Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D5</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR2H>
<UBRR2L>
<NAME>UBRR2L</NAME>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$D4</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR2L>
</USART2>
<USART3>
<LIST>[UDR3:UCSR3A:UCSR3B:UCSR3C:UBRR3H:UBRR3L]</LIST>
<LINK>[UBRR3H:UBRR3L]</LINK>
<ICON>io_com.bmp</ICON>
<ID/>
<TEXT>The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica</TEXT>
<UDR3>
<NAME>UDR3</NAME>
<DESCRIPTION>USART I/O Data Register</DESCRIPTION>
<TEXT>The UDR3 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$136</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UDR3-7</NAME>
<DESCRIPTION>USART I/O Data Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UDR3-6</NAME>
<DESCRIPTION>USART I/O Data Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDR3-5</NAME>
<DESCRIPTION>USART I/O Data Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UDR3-4</NAME>
<DESCRIPTION>USART I/O Data Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UDR3-3</NAME>
<DESCRIPTION>USART I/O Data Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UDR3-2</NAME>
<DESCRIPTION>USART I/O Data Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UDR3-1</NAME>
<DESCRIPTION>USART I/O Data Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UDR3-0</NAME>
<DESCRIPTION>USART I/O Data Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UDR3>
<UCSR3A>
<NAME>UCSR3A</NAME>
<DESCRIPTION>USART Control and Status Register A</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$130</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXC3</NAME>
<DESCRIPTION>USART Receive Complete</DESCRIPTION>
<TEXT>This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXC3</NAME>
<DESCRIPTION>USART Transmitt Complete</DESCRIPTION>
<TEXT>This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRE3</NAME>
<DESCRIPTION>USART Data Register Empty</DESCRIPTION>
<TEXT>This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>FE3</NAME>
<DESCRIPTION>Framing Error</DESCRIPTION>
<TEXT>This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>DOR3</NAME>
<DESCRIPTION>Data overRun</DESCRIPTION>
<TEXT>This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. </TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UPE3</NAME>
<DESCRIPTION>Parity Error</DESCRIPTION>
<TEXT>This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>U2X3</NAME>
<DESCRIPTION>Double the USART transmission speed</DESCRIPTION>
<TEXT>This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>MPCM3</NAME>
<DESCRIPTION>Multi-processor Communication Mode</DESCRIPTION>
<TEXT>This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR3A>
<UCSR3B>
<NAME>UCSR3B</NAME>
<DESCRIPTION>USART Control and Status Register B</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$131</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>RXCIE3</NAME>
<DESCRIPTION>RX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>TXCIE3</NAME>
<DESCRIPTION>TX Complete Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UDRIE3</NAME>
<DESCRIPTION>USART Data register Empty Interrupt Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT5>
<BIT4>
<NAME>RXEN3</NAME>
<DESCRIPTION>Receiver Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>TXEN3</NAME>
<DESCRIPTION>Transmitter Enable</DESCRIPTION>
<TEXT>Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ32</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>The UCSZ3 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>RXB83</NAME>
<DESCRIPTION>Receive Data Bit 8</DESCRIPTION>
<TEXT>RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.</TEXT>
<ACCESS>R</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>TXB83</NAME>
<DESCRIPTION>Transmit Data Bit 8</DESCRIPTION>
<TEXT>TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.</TEXT>
<ACCESS>W</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR3B>
<UCSR3C>
<NAME>UCSR3C</NAME>
<DESCRIPTION>USART Control and Status Register C</DESCRIPTION>
<TEXT/>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$132</MEM_ADDR>
<ICON>io_flag.bmp</ICON>
<DISPLAY_BITS>Y</DISPLAY_BITS>
<BIT7>
<NAME>UMSEL31</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UMSEL30</NAME>
<DESCRIPTION>USART Mode Select</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UPM31</NAME>
<DESCRIPTION>Parity Mode Bit 1</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UPM30</NAME>
<DESCRIPTION>Parity Mode Bit 0</DESCRIPTION>
<TEXT>This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>USBS3</NAME>
<DESCRIPTION>Stop Bit Select</DESCRIPTION>
<TEXT>0: 1-bit. 1: 2-bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UCSZ31</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UCSZ30</NAME>
<DESCRIPTION>Character Size</DESCRIPTION>
<TEXT>Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>1</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UCPOL3</NAME>
<DESCRIPTION>Clock Polarity</DESCRIPTION>
<TEXT>This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).</TEXT>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UCSR3C>
<UBRR3H>
<NAME>UBRR3H</NAME>
<DESCRIPTION>USART Baud Rate Register High Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$135</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT3>
<NAME>UBRR11</NAME>
<DESCRIPTION>USART Baud Rate Register bit 11</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR10</NAME>
<DESCRIPTION>USART Baud Rate Register bit 10</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR9</NAME>
<DESCRIPTION>USART Baud Rate Register bit 9</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR8</NAME>
<DESCRIPTION>USART Baud Rate Register bit 8</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR3H>
<UBRR3L>
<NAME>UBRR3L</NAME>
<DESCRIPTION>USART Baud Rate Register Low Byte</DESCRIPTION>
<TEXT>This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.</TEXT>
<IO_ADDR>NA</IO_ADDR>
<MEM_ADDR>$134</MEM_ADDR>
<ICON>io_com.bmp</ICON>
<DISPLAY_BITS>N</DISPLAY_BITS>
<BIT7>
<NAME>UBRR7</NAME>
<DESCRIPTION>USART Baud Rate Register bit 7</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT7>
<BIT6>
<NAME>UBRR6</NAME>
<DESCRIPTION>USART Baud Rate Register bit 6</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT6>
<BIT5>
<NAME>UBRR5</NAME>
<DESCRIPTION>USART Baud Rate Register bit 5</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT5>
<BIT4>
<NAME>UBRR4</NAME>
<DESCRIPTION>USART Baud Rate Register bit 4</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT4>
<BIT3>
<NAME>UBRR3</NAME>
<DESCRIPTION>USART Baud Rate Register bit 3</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT3>
<BIT2>
<NAME>UBRR2</NAME>
<DESCRIPTION>USART Baud Rate Register bit 2</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT2>
<BIT1>
<NAME>UBRR1</NAME>
<DESCRIPTION>USART Baud Rate Register bit 1</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT1>
<BIT0>
<NAME>UBRR0</NAME>
<DESCRIPTION>USART Baud Rate Register bit 0</DESCRIPTION>
<TEXT/>
<ACCESS>RW</ACCESS>
<INIT_VAL>0</INIT_VAL>
</BIT0>
</UBRR3L>
</USART3>
</IO_MODULE><ICE_SETTINGS><MODULE_LIST>[SIMULATOR:JTAGICEmkII:STK500_2:AVRISPmkII]</MODULE_LIST><SIMULATOR>
<CoreID>AVRSimCoreV2.SimCoreV2</CoreID>
<MemoryID>AVRSimMemory8bit.SimMemory8bit</MemoryID>
<InterruptID>AVRSimInterrupt.SimInterrupt</InterruptID>
<EEINTERRUPT>0x3c</EEINTERRUPT>
<EEAR_EXTRA_BIT>0</EEAR_EXTRA_BIT>
<NmbIOModules>35</NmbIOModules>
<PORTA>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTA>
<PORTB>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTB>
<PORTC>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTC>
<PORTD>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTD>
<PORTE>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTE>
<PORTF>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTF>
<PORTG>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTG>
<PORTH>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTH>
<PORTJ>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTJ>
<PORTK>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTK>
<PORTL>
<ID>AVRSimIOPort.SimIOPort</ID>
<TOGGLE_PIN>Y</TOGGLE_PIN>
</PORTL>
<PININT0>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x12</IntVector>
<EnableIOAdr>0x48</EnableIOAdr>
<EnableMask>0x01</EnableMask>
<FlagIOAdr>0x1B</FlagIOAdr>
<FlagMask>0x01</FlagMask>
<PCMaskIOAdr>0x4b</PCMaskIOAdr>
<ExtPinIOAdr>0x03</ExtPinIOAdr>
<ExtPinMask>0xff</ExtPinMask>
</PININT0>
<PININT1>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x14</IntVector>
<EnableIOAdr>0x48</EnableIOAdr>
<EnableMask>0x02</EnableMask>
<FlagIOAdr>0x1B</FlagIOAdr>
<FlagMask>0x02</FlagMask>
<ExtPinIOAdr>0xe3</ExtPinIOAdr>
<ExtPinMask>0xff</ExtPinMask>
<PCMaskIOAdr>0x4c</PCMaskIOAdr>
</PININT1>
<PININT2>
<ID>AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt</ID>
<IntVector>0x16</IntVector>
<EnableIOAdr>0x48</EnableIOAdr>
<EnableMask>0x04</EnableMask>
<FlagIOAdr>0x1B</FlagIOAdr>
<FlagMask>0x04</FlagMask>
<ExtPinIOAdr>0xe6</ExtPinIOAdr>
<ExtPinMask>0xff</ExtPinMask>
<PCMaskIOAdr>0x4d</PCMaskIOAdr>
</PININT2>
<EXTINT0>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x02</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x01</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x01</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x01</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT0>
<EXTINT1>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x04</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x02</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x02</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x02</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT1>
<EXTINT2>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x06</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x04</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x04</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x04</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0x30</SenseMask>
</EXTINT2>
<EXTINT3>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x08</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x08</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x08</FlagMask>
<ExtPinIOAdr>0x09</ExtPinIOAdr>
<ExtPinMask>0x08</ExtPinMask>
<SenseIOAdr>0x49</SenseIOAdr>
<SenseMask>0xc0</SenseMask>
</EXTINT3>
<EXTINT4>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0a</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x10</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x10</FlagMask>
<ExtPinIOAdr>0x0C</ExtPinIOAdr>
<ExtPinMask>0x10</ExtPinMask>
<SenseIOAdr>0x4a</SenseIOAdr>
<SenseMask>0x03</SenseMask>
</EXTINT4>
<EXTINT5>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0c</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x20</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x20</FlagMask>
<ExtPinIOAdr>0x0C</ExtPinIOAdr>
<ExtPinMask>0x20</ExtPinMask>
<SenseIOAdr>0x4a</SenseIOAdr>
<SenseMask>0x0c</SenseMask>
</EXTINT5>
<EXTINT6>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x0e</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x40</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x40</FlagMask>
<ExtPinIOAdr>0x0C</ExtPinIOAdr>
<ExtPinMask>0x40</ExtPinMask>
<SenseIOAdr>0x4a</SenseIOAdr>
<SenseMask>0x30</SenseMask>
</EXTINT6>
<EXTINT7>
<ID>AVRSimIOExtInterrupt.SimIOExtInterrupt</ID>
<IntVector>0x10</IntVector>
<EnableIOAdr>0x1d</EnableIOAdr>
<EnableMask>0x80</EnableMask>
<FlagIOAdr>0x1c</FlagIOAdr>
<FlagMask>0x80</FlagMask>
<ExtPinIOAdr>0x0C</ExtPinIOAdr>
<ExtPinMask>0x80</ExtPinMask>
<SenseIOAdr>0x4a</SenseIOAdr>
<SenseMask>0xc0</SenseMask>
</EXTINT7>
<TIMER0>
<ID>AvrSimIOtim8pwmsync2.tim8pwmsync2</ID>
<CompAVector>0x2A</CompAVector>
<CompBVector>0x2C</CompBVector>
<OvfVector>0x2E</OvfVector>
<OCnAport>PORTB</OCnAport>
<OCnAbit>7</OCnAbit>
<OCnBport>PORTG</OCnBport>
<OCnBbit>5</OCnBbit>
</TIMER0>
<TIMER1>
<ID>AvrMasterTimer.MasterTimer</ID>
<IcpVector>0x20</IcpVector>
<CompAVector>0x22</CompAVector>
<CompBVector>0x24</CompBVector>
<CompCVector>0x26</CompCVector>
<OvfVector>0x28</OvfVector>
<CountPinAdr>0x09</CountPinAdr>
<CountPinMask>0x40</CountPinMask>
<IcpPinAdr>0x09</IcpPinAdr>
<IcpPinMask>0x10</IcpPinMask>
<OutputAAdr>0x05</OutputAAdr>
<OutputAMask>0x20</OutputAMask>
<OutputBAdr>0x05</OutputBAdr>
<OutputBMask>0x40</OutputBMask>
<OutputCAdr>0x05</OutputCAdr>
<OutputCMask>0x80</OutputCMask>
<OCFA>TIFR1/OCF1A</OCFA>
<OCFB>TIFR1/OCF1B</OCFB>
<OCFC>TIFR1/OCF1C</OCFC>
<Prescaler>1:8:64:256:1024</Prescaler>
<PSRregister>0x23</PSRregister>
<PSRbitmask>0x01</PSRbitmask>
</TIMER1>
<TIMER2>
<ID>AvrMasterTimer.MasterTimer</ID>
<CompAVector>0x1a</CompAVector>
<CompBVector>0x1c</CompBVector>
<OvfVector>0x1e</OvfVector>
<OCnAport>PORTB</OCnAport>
<OCnAbit>4</OCnAbit>
<OCnBport>PORTH</OCnBport>
<OCnBbit>6</OCnBbit>
<Prescaler>1:8:64:256:1024</Prescaler>
</TIMER2>
<TIMER3>
<ID>AvrMasterTimer.MasterTimer</ID>
<IcpVector>0x3E</IcpVector>
<CompAVector>0x40</CompAVector>
<CompBVector>0x42</CompBVector>
<CompCVector>0x44</CompCVector>
<OvfVector>0x46</OvfVector>
<CountPinAdr>0x0C</CountPinAdr>
<CountPinMask>0x40</CountPinMask>
<IcpPinAdr>0x0C</IcpPinAdr>
<IcpPinMask>0x80</IcpPinMask>
<OutputAAdr>0x0e</OutputAAdr>
<OutputAMask>0x08</OutputAMask>
<OutputBAdr>0x0e</OutputBAdr>
<OutputBMask>0x10</OutputBMask>
<OutputCAdr>0x0e</OutputCAdr>
<OutputCMask>0x20</OutputCMask>
<OCFA>TIFR3/OCF3A</OCFA>
<OCFB>TIFR3/OCF3B</OCFB>
<OCFC>TIFR3/OCF3C</OCFC>
<Prescaler>1:8:64:256:1024</Prescaler>
<PSRregister>0x23</PSRregister>
<PSRbitmask>0x01</PSRbitmask>
</TIMER3>
<TIMER4>
<ID>AvrMasterTimer.MasterTimer</ID>
<IcpVector>0x52</IcpVector>
<CompAVector>0x54</CompAVector>
<CompBVector>0x56</CompBVector>
<CompCVector>0x58</CompCVector>
<OvfVector>0x5a</OvfVector>
<CountPinAdr>0xe2</CountPinAdr>
<CountPinMask>0x80</CountPinMask>
<IcpPinAdr>0xe9</IcpPinAdr>
<IcpPinMask>0x01</IcpPinMask>
<OutputAAdr>0xe0</OutputAAdr>
<OutputAMask>0x10</OutputAMask>
<OutputBAdr>0xe0</OutputBAdr>
<OutputBMask>0x20</OutputBMask>
<OutputCAdr>0xe0</OutputCAdr>
<OutputCMask>0x40</OutputCMask>
<OCFA>TIFR4/OCF4A</OCFA>
<OCFB>TIFR4/OCF4B</OCFB>
<OCFC>TIFR4/OCF4C</OCFC>
<Prescaler>1:8:64:256:1024</Prescaler>
<PSRregister>0x23</PSRregister>
<PSRbitmask>0x01</PSRbitmask>
</TIMER4>
<TIMER5>
<ID>AvrMasterTimer.MasterTimer</ID>
<IcpVector>0x5c</IcpVector>
<CompAVector>0x5e</CompAVector>
<CompBVector>0x60</CompBVector>
<CompCVector>0x62</CompCVector>
<OvfVector>0x64</OvfVector>
<CountPinAdr>0xe9</CountPinAdr>
<CountPinMask>0x04</CountPinMask>
<IcpPinAdr>0xe9</IcpPinAdr>
<IcpPinMask>0x02</IcpPinMask>
<OutputAAdr>0xe9</OutputAAdr>
<OutputAMask>0x80</OutputAMask>
<OutputBAdr>0xe9</OutputBAdr>
<OutputBMask>0x10</OutputBMask>
<OutputCAdr>0xe9</OutputCAdr>
<OutputCMask>0x20</OutputCMask>
<OCFA>TIFR5/OCF5A</OCFA>
<OCFB>TIFR5/OCF5B</OCFB>
<OCFC>TIFR5/OCF5C</OCFC>
<Prescaler>1:8:64:256:1024</Prescaler>
<PSRregister>0x23</PSRregister>
<PSRbitmask>0x01</PSRbitmask>
</TIMER5>
<SPM>
<ID>AVRSimIOSPM.SimIOSPM</ID>
<IntVector>0x50</IntVector>
</SPM>
<SPI>
<ID>AVRSimIOSpi.SimIOSpi</ID>
<IntVector>0x30</IntVector>
<SCKAddress>0x03</SCKAddress>
<SCKMask>0x02</SCKMask>
<MISOAddress>0x03</MISOAddress>
<MISOMask>0x08</MISOMask>
<MOSIAddress>0x03</MOSIAddress>
<MOSIMask>0x04</MOSIMask>
<SSAddress>0x03</SSAddress>
<DIRAddress>0x04</DIRAddress>
<SSMask>0x01</SSMask>
</SPI>
<USART0>
<ID>AVRSimIOUsart.SimIOUsart</ID>
<RXVector>0x32</RXVector>
<TXVector>0x36</TXVector>
<UDREVector>0x34</UDREVector>
<TXPinAddress>0x0c</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0x0c</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</USART0>
<USART1>
<ID>AVRSimIOUsart.SimIOUsart</ID>
<RXVector>0x48</RXVector>
<TXVector>0x4C</TXVector>
<UDREVector>0x4A</UDREVector>
<TXPinAddress>0x09</TXPinAddress>
<TXPinMask>0x08</TXPinMask>
<RXPinAddress>0x09</RXPinAddress>
<RXPinMask>0x04</RXPinMask>
</USART1>
<USART2>
<ID>AVRSimIOUsart.SimIOUsart</ID>
<RXVector>0x66</RXVector>
<TXVector>0x6a</TXVector>
<UDREVector>0x68</UDREVector>
<TXPinAddress>0xe0</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0xe0</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</USART2>
<USART3>
<ID>AVRSimIOUsart.SimIOUsart</ID>
<RXVector>0x6c</RXVector>
<TXVector>0x70</TXVector>
<UDREVector>0x6e</UDREVector>
<TXPinAddress>0xe3</TXPinAddress>
<TXPinMask>0x02</TXPinMask>
<RXPinAddress>0xe3</RXPinAddress>
<RXPinMask>0x01</RXPinMask>
</USART3>
<ANALOGCOMP>
<ID>AVRSimAC.SimIOAC</ID>
<IntVector>0x38</IntVector>
</ANALOGCOMP>
<ADC>
<ID>AVRSimADC.SimADC</ID>
<IntVector>0x3A</IntVector>
</ADC>
<TWI>
<ID>AvrSimTWI.SimTWI</ID>
<IntVector>0x4E</IntVector>
</TWI>
<WATCHDOG>
<ID>AvrMasterTimer.MasterTimer</ID>
<Version>0</Version>
<PrescaleArray>16384:32768:65536:131072:262144:524288:1048576:2097152</PrescaleArray>
</WATCHDOG>
<DEFAULT_SETTINGS>
<HighFuse>0xFF</HighFuse>
<ExtendedFuse>0xff</ExtendedFuse>
<LowFuse>0xFF</LowFuse>
<Lockbit>0xFF</Lockbit>
</DEFAULT_SETTINGS>
</SIMULATOR>
<JTAGICEmkII>
<ID>0x0960803F</ID>
<Interface>JTAG</Interface>
<!--Bit 0 in byte 0 is I/O location, bit 7 in byte 7 is I/O location 63-->
<ucRead>0xFF,0xFF,0xFF,0xFF,0xFF,0x3D,0xB9,0xF8</ucRead>
<ucWrite>0xFF,0xFF,0x1F,0xE0,0xFF,0x1D,0xA9,0xF8</ucWrite>
<ucReadShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucReadShadow>
<ucWriteShadow>0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00</ucWriteShadow>
<!--Bit 0 in byte 0 is extended I/O location, bit 7 in byte 7 is I/O location 63-->
<ucExtRead>0x73,0xFF,0x3F,0xFF,0xF7,0x3F,0xF7,0x3F,0xF7,0x3F,0x5F,0x3F,0x37,0x37,0x37,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF7, 0x3F, 0x36,0x00</ucExtRead>
<ucExtWrite>0x73,0xFF,0x3F,0xF8,0xF7,0x3F,0xF7,0x3F,0xF7,0x3F,0x5F,0x2F,0x36,0x36,0x36,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF7, 0x3F, 0x36,0x00</ucExtWrite>
<ucExtReadShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtReadShadow>
<ucExtWriteShadow>0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00</ucExtWriteShadow>
<!--Register locations etc.-->
<ucIDRAddress>0x31</ucIDRAddress>
<ucSPMCAddress>0x57</ucSPMCAddress>
<!--no longer needed build 356 ucRAMPZAddress>0x3B</ucRAMPZAddress -->
<ulFlashPageSize>0x0100</ulFlashPageSize>
<ulEepromPageSize>0x0008</ulEepromPageSize>
<ulBootAddress>0x7E00</ulBootAddress>
<!-- No longer needed build 356
<BootAddress11>0x7E00</BootAddress11>
<BootAddress10>0x7C00</BootAddress10>
<BootAddress01>0x7800</BootAddress01>
<BootAddress00>0x7000</BootAddress00>
-->
<ucUpperExtIOLoc>0x0136</ucUpperExtIOLoc>
<!--no longer needed build 356 ulFlashSize>0x10000</ulFlashSize -->
<ulRegStart>0x0000,32</ulRegStart>
<ulIoStart>0x0020,64</ulIoStart>
<!--Other stuff-->
<DWENmaskExt>0x00</DWENmaskExt>
<DWENmaskHigh>0x00</DWENmaskHigh>
<DWENmaskLow>0x00</DWENmaskLow>
<!--no longer needed build 356
<SPIENmaskExt>0x00</SPIENmaskExt>
<SPIENmaskHigh>0x20</SPIENmaskHigh>
<SPIENmaskLow>0x00</SPIENmaskLow>
-->
<ucEepromInst>0x00</ucEepromInst>
<ucFlashInst>0x00</ucFlashInst>
<!--no longer needed build 356
<ucSPHaddr>0x3E</ucSPHaddr>
<ucSPLaddr>0x3D</ucSPLaddr>
-->
<DWdatareg>0x00</DWdatareg>
<DWbasePC>0x00</DWbasePC>
<PCMaskExtended>0</PCMaskExtended>
<PCMaskHigh>0</PCMaskHigh>
<Osccalshared>0x00</Osccalshared>
<ucAllowFullPageBitstream>0x00</ucAllowFullPageBitstream>
<uiStartSmallestBootLoaderSection>0x00</uiStartSmallestBootLoaderSection>
<ucUseJTAGID>0x01</ucUseJTAGID>
<EECRAddress>0x3F</EECRAddress>
<EnablePageProgramming>1</EnablePageProgramming>
<CacheType>0</CacheType>
<ResetType>0</ResetType>
<bUseProgIfc>1</bUseProgIfc>
</JTAGICEmkII>
<STK500_2><IspEnterProgMode><timeout>200</timeout><stabDelay>100</stabDelay><cmdexeDelay>25</cmdexeDelay><synchLoops>32</synchLoops><byteDelay>0</byteDelay><pollIndex>3</pollIndex><pollValue>0x53</pollValue></IspEnterProgMode><IspLeaveProgMode><preDelay>1</preDelay><postDelay>1</postDelay></IspLeaveProgMode><IspChipErase><eraseDelay>55</eraseDelay><pollMethod>1</pollMethod></IspChipErase><IspProgramFlash><mode>0x41</mode><blockSize>256</blockSize><delay>10</delay><cmd1>0x40</cmd1><cmd2>0x4C</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramFlash><IspProgramEeprom><mode>0x41</mode><blockSize>8</blockSize><delay>10</delay><cmd1>0xC1</cmd1><cmd2>0xC2</cmd2><cmd3>0x00</cmd3><pollVal1>0x00</pollVal1><pollVal2>0x00</pollVal2></IspProgramEeprom><IspReadFlash><blockSize>256</blockSize></IspReadFlash><IspReadEeprom><blockSize>256</blockSize></IspReadEeprom><IspReadFuse><pollIndex>4</pollIndex></IspReadFuse><IspReadLock><pollIndex>4</pollIndex></IspReadLock><IspReadSign><pollIndex>4</pollIndex></IspReadSign><IspReadOsccal><pollIndex>4</pollIndex></IspReadOsccal><PPControlStack>0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00</PPControlStack><PpEnterProgMode><stabDelay>100</stabDelay><progModeDelay>0</progModeDelay><latchCycles>5</latchCycles><toggleVtg>1</toggleVtg><powerOffDelay>15</powerOffDelay><resetDelayMs>1</resetDelayMs><resetDelayUs>0</resetDelayUs></PpEnterProgMode><PpLeaveProgMode><stabDelay>15</stabDelay><resetDelay>15</resetDelay></PpLeaveProgMode><PpChipErase><pulseWidth>0</pulseWidth><pollTimeout>10</pollTimeout></PpChipErase><PpProgramFlash><pollTimeout>5</pollTimeout><mode>0x01</mode><blockSize>256</blockSize></PpProgramFlash><PpReadFlash><blockSize>256</blockSize></PpReadFlash><PpProgramEeprom><pollTimeout>5</pollTimeout><mode>0x07</mode><blockSize>256</blockSize></PpProgramEeprom><PpReadEeprom><blockSize>256</blockSize></PpReadEeprom><PpProgramFuse><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramFuse><PpProgramLock><pulseWidth>0</pulseWidth><pollTimeout>5</pollTimeout></PpProgramLock></STK500_2><AVRISPmkII/>
</ICE_SETTINGS></AVRPART>
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