Plan 9 from Bell Labs’s /usr/web/sources/contrib/rsc/86b/inst.txt

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


37				AAA						ASCII adjust AL after addition
D5 0A			AAD						ASCII adjust AX before division
D4 0A			AAM						ASCII adjust AX after multiply
3F				AAS						ASCII adjust AL after subtraction
14 ib			ADC AL,imm8				Add with carry immediate byte to AL
15 iw			ADC AX,imm16			Add with carry immediate word to AX
15 id			ADC EAX,imm32			Add with carry immediate dword to EAX
80 /2 ib		ADC r/m8,imm8			Add with carry immediate byte to r/m 
81 /2 iw		ADC r/m16,imm16			Add with carry immediate word to r/m 
81 /2 id		ADC r/m32,imm32			Add with CF immediate dword to r/m 
83 /2 ib		ADC r/m16,imm8			Add with CF sign-extended immediate 
83 /2 ib		ADC r/m32,imm8			Add with CF sign-extended immediate 
10 /r			ADC r/m8,r8				Add with carry byte register to r/m 
11 /r			ADC r/m16,r16			Add with carry word register to r/m 
11 /r			ADC r/m32,r32			Add with CF dword register to r/m dword
12 /r			ADC r8,r/m8				Add with carry r/m byte to byte 
13 /r			ADC r16,r/m16			Add with carry r/m word to word 
13 /r			ADC r32,r/m32			Add with CF r/m dword to dword register
04 ib			ADD AL,imm8				Add immediate byte to AL
05 iw			ADD AX,imm16			Add immediate word to AX
05 id			ADD EAX,imm32			Add immediate dword to EAX
80 /0 ib		ADD r/m8,imm8			Add immediate byte to r/m byte
81 /0 iw		ADD r/m16,imm16			Add immediate word to r/m word
81 /0 id		ADD r/m32,imm32			Add immediate dword to r/m dword
83 /0 ib		ADD r/m16,imm8			Add sign-extended immediate byte 
83 /0 ib		ADD r/m32,imm8			Add sign-extended immediate byte 
00 /r			ADD r/m8,r8				Add byte register to r/m byte
01 /r			ADD r/m16,r16			Add word register to r/m word
01 /r			ADD r/m32,r32			Add dword register to r/m dword
02 /r			ADD r8,r/m8				Add r/m byte to byte register
03 /r			ADD r16,r/m16			Add r/m word to word register
03 /r			ADD r32,r/m32			Add r/m dword to dword register
24 ib			AND AL,imm8				AND immediate byte to AL
25 iw			AND AX,imm16			AND immediate word to AX
25 id			AND EAX,imm32			AND immediate dword to EAX
80 /4 ib		AND r/m8,imm8			AND immediate byte to r/m byte
81 /4 iw		AND r/m16,imm16			AND immediate word to r/m word
81 /4 id		AND r/m32,imm32			AND immediate dword to r/m dword
83 /4 ib		AND r/m16,imm8			AND sign-extended immediate byte 
83 /4 ib		AND r/m32,imm8			AND sign-extended immediate byte 
20 /r			AND r/m8,r8				AND byte register to r/m byte
21 /r			AND r/m16,r16			AND word register to r/m word
21 /r			AND r/m32,r32			AND dword register to r/m dword
22 /r			AND r8,r/m8				AND r/m byte to byte register
23 /r			AND r16,r/m16			AND r/m word to word register
23 /r			AND r32,r/m32			AND r/m dword to dword register
63 /r			ARPL r/m16,r16			Adjust RPL of r/m16 to not 
62 /r			BOUND r16,m16&16		Check if r16 is within bounds 
62 /r			BOUND r32,m32&32		Check if r32 is within bounds 
0F BC			BSF r16,r/m16			Bit scan forward on r/m word
0F BC			BSF r32,r/m32			Bit scan forward on r/m dword
0F BD			BSR r16,r/m16			Bit scan reverse on r/m word
0F BD			BSR r32,r/m32			Bit scan reverse on r/m dword
0F A3			BT r/m16,r16			Save bit in carry flag
0F A3			BT r/m32,r32			Save bit in carry flag
0F BA /4 ib		BT r/m16,imm8			Save bit in carry flag
0F BA /4 ib		BT r/m32,imm8			Save bit in carry flag
0F BB			BTC r/m16,r16			Save bit in carry flag and complement
0F BB			BTC r/m32,r32			Save bit in carry flag and complement
0F BA /7 ib		BTC r/m16,imm8			Save bit in carry flag and complement
0F BA /7 ib		BTC r/m32,imm8			Save bit in carry flag and complement
0F B3			BTR r/m16,r16			Save bit in carry flag and reset
0F B3			BTR r/m32,r32			Save bit in carry flag and reset
0F BA /6 ib		BTR r/m16,imm8			Save bit in carry flag and reset
0F BA /6 ib		BTR r/m32,imm8			Save bit in carry flag and reset
0F AB			BTS r/m16,r16			Save bit in carry flag and set
0F AB			BTS r/m32,r32			Save bit in carry flag and set
0F BA /5 ib		BTS r/m16,imm8			Save bit in carry flag and set
0F BA /5 ib		BTS r/m32,imm8			Save bit in carry flag and set
98				CBW						AX <- sign-extend of AL
98				CWDE					EAX <- sign-extend of AX
F8				CLC						Clear carry flag
FC				CLD						Clear direction flag; SI and DI 
FA				CLI						Clear interrupt flag; interrupts disabled
0F 06			CLTS					Clear task-switched flag
F5				CMC						Complement carry flag
3C ib			CMP AL,imm8				Compare immediate byte to AL
3D iw			CMP AX,imm16			Compare immediate word to AX
3D id			CMP EAX,imm32			Compare immediate dword to EAX
80 /7 ib		CMP r/m8,imm8			Compare immediate byte to r/m 
81 /7 iw		CMP r/m16,imm16			Compare immediate word to r/m 
81 /7 id		CMP r/m32,imm32			Compare immediate dword to r/m 
83 /7 ib		CMP r/m16,imm8			Compare sign extended immediate 
83 /7 ib		CMP r/m32,imm8			Compare sign extended immediate 
38 /r			CMP r/m8,r8				Compare byte register to r/m 
39 /r			CMP r/m16,r16			Compare word register to r/m 
39 /r			CMP r/m32,r32			Compare dword register to r/m 
3A /r			CMP r8,r/m8				Compare r/m byte to byte 
3B /r			CMP r16,r/m16			Compare r/m word to word 
3B /r			CMP r32,r/m32			Compare r/m dword to dword 
A6				CMPS m8,m8				Compare bytes ES:[(E)DI] (second 
A7				CMPS m16,m16			Compare words ES:[(E)DI] (second 
A7				CMPS m32,m32			Compare dwords ES:[(E)DI] 
A6				CMPSB					Compare bytes ES:[(E)DI] with 
A7				CMPSW					Compare words ES:[(E)DI] with 
A7				CMPSD					Compare dwords ES:[(E)DI] with 
99				CWD						DX:AX <- sign-extend of AX
99				CDQ						EDX:EAX <- sign-extend of EAX
27				DAA						Decimal adjust AL after addition
2F				DAS						Decimal adjust AL after subtraction
FE /1			DEC r/m8				Decrement r/m byte by 1
FF /1			DEC r/m16				Decrement r/m word by 1
FF/1			DEC r/m32				Decrement r/m dword by 1
48 +r			DEC r16					Decrement word register by 1
48 +r			DEC r32					Decrement dword register by 1
F6 /6			DIV AL,r/m8				Unsigned divide AX by r/m byte 
F7 /6			DIV AX,r/m16			Unsigned divide DX:AX by r/m 
F7 /6			DIV EAX,r/m32			Unsigned divide EDX:EAX by r/m 
C8 iw 00		ENTER imm16,0			Make procedure stack frame
C8 iw 01		ENTER imm16,1			Make stack frame for procedure 
C8 iw ib		ENTER imm16,imm8		Make stack frame for 
F4				HLT						Halt
F6 /7			IDIV r/m8				Signed divide AX by r/m byte 
F7 /7			IDIV AX,r/m16			Signed divide DX:AX by EA word 
F7 /7			IDIV EAX,r/m32			Signed divide EDX:EAX by DWORD 
F6 /5			IMUL r/m8				AX<- AL * r/m byte
F7 /5			IMUL r/m16				DX:AX <- AX * r/m word
F7 /5			IMUL r/m32				EDX:EAX <- EAX * r/m dword
0F AF /r		IMUL r16,r/m16			word register <- word 
0F AF /r		IMUL r32,r/m32			dword register <- dword 
6B /r ib		IMUL r16,r/m16,imm8		word register <- r/m16 * 
6B /r ib		IMUL r32,r/m32,imm8		dword register <- r/m32 * 
6B /r ib		IMUL r16,imm8			word register <- word 
6B /r ib		IMUL r32,imm8			dword register <- dword 
69 /r iw		IMUL r16,r/m16,imm16	word register <- r/m16 * 
69 /r id		IMUL r32,r/m32,imm32	dword register <- r/m32 * 
69 /r iw		IMUL r16,imm16			word register <- r/m16 * 
69 /r id		IMUL r32,imm32			dword register <- r/m32 * 
E4 ib			IN AL,imm8				Input byte from immediate port 
E5 ib			IN AX,imm8				Input word from immediate port 
E5 ib			IN EAX,imm8				Input dword from immediate port 
EC				IN AL,DX				Input byte from port DX into AL
ED				IN AX,DX				Input word from port DX into AX
ED				IN EAX,DX				Input dword from port DX into 
FE /0			INC r/m8				Increment r/m byte by 1
FF /0			INC r/m16				Increment r/m word by 1
FF /6			INC r/m32				Increment r/m dword by 1
40 +r			INC r16					Increment word register by 1
40 +r			INC r32					Increment dword register by 1
6C				INS r/m8,DX				Input byte from port DX into ES:(E)DI
6D				INS r/m16,DX			Input word from port DX into ES:(E)DI
6D				INS r/m32,DX			Input dword from port DX into ES:(E)DI
6C				INSB					Input byte from port DX into ES:(E)DI
6D				INSW					Input word from port DX into ES:(E)DI
6D				INSD					Input dword from port DX into ES:(E)DI
CC				INT 3					Interrupt 3--trap to debugger
CC				INT 3					Interrupt 3--Protected Mode, same 
CC				INT 3					Interrupt 3--Protected Mode, more 
CC				INT 3					Interrupt 3--from V86 mode to PL 0
CC				INT 3					Interrupt 3--Protected Mode, via 
CD ib			INT imm8				Interrupt numbered by immediate 
CD ib			INT imm8				Interrupt--Protected Mode, same 
CD ib			INT imm8				Interrupt--Protected Mode, more 
CD ib			INT imm8				Interrupt--from V86 mode to PL 0
CD ib			INT imm8				Interrupt--Protected Mode, via task 
CE				INTO					Interrupt 4--if overflow flag is 1
CE				INTO					Interrupt 4--Protected Mode, same 
CE				INTO					Interrupt 4--Protected Mode, more 
CE				INTO					Interrupt 4--from V86 mode to PL 0
CE				INTO					Interrupt 4--Protected Mode, via 
CF				IRET					Interrupt return (far return and pop 
CF				IRET					Interrupt return to lesser privilege
CF				IRET					Interrupt return, different task (NT = 1)
CF				IRETD					Interrupt return (far return and pop 
CF				IRETD					Interrupt return to lesser privilege
CF				IRETD					Interrupt return to V86 mode
CF				IRETD					Interrupt return, different task (NT = 1)
77 cb			JA rel8					Jump short if above (CF=0 and 
73 cb			JAE rel8				Jump short if above or equal 
72 cb			JB rel8					Jump short if below (CF=1)
76 cb			JBE rel8				Jump short if below or equal 
72 cb			JC rel8					Jump short if carry (CF=1)
E3 cb			JCXZ rel8				Jump short if CX register is 0
E3 cb			JECXZ rel8				Jump short if ECX register is 0
74 cb			JE rel8					Jump short if equal (ZF=1)
74 cb			JZ rel8					Jump short if 0 (ZF=1)
7F cb			JG rel8					Jump short if greater (ZF=0 and 
7D cb			JGE rel8				Jump short if greater or equal 
7C cb			JL rel8					Jump short if less (SFOF)
7E cb			JLE rel8				Jump short if less or equal 
76 cb			JNA rel8				Jump short if not above (CF=1 or 
72 cb			JNAE rel8				Jump short if not above or equal 
73 cb			JNB rel8				Jump short if not below (CF=0)
77 cb			JNBE rel8				Jump short if not below or equal 
73 cb			JNC rel8				Jump short if not carry (CF=0)
75 cb			JNE rel8				Jump short if not equal (ZF=0)
7E cb			JNG rel8				Jump short if not greater (ZF=1 
7C cb			JNGE rel8				Jump short if not greater or 
7D cb			JNL rel8				Jump short if not less (SF=OF)
7F cb			JNLE rel8				Jump short if not less or equal 
71 cb			JNO rel8				Jump short if not overflow 
7B cb			JNP rel8				Jump short if not parity (PF=0)
79 cb			JNS rel8				Jump short if not sign (SF=0)
75 cb			JNZ rel8				Jump short if not zero (ZF=0)
70 cb			JO rel8					Jump short if overflow (OF=1)
7A cb			JP rel8					Jump short if parity (PF=1)
7A cb			JPE rel8				Jump short if parity even (PF=1)
7B cb			JPO rel8				Jump short if parity odd (PF=0)
78 cb			JS rel8					Jump short if sign (SF=1)
74 cb			JZ rel8					Jump short if zero (ZF = 1)
0F 87 cw/cd		JA rel16/32				Jump near if above (CF=0 and 
0F 83 cw/cd		JAE rel16/32			Jump near if above or equal 
0F 82 cw/cd		JB rel16/32				Jump near if below (CF=1)
0F 86 cw/cd		JBE rel16/32			Jump near if below or equal 
0F 82 cw/cd		JC rel16/32				Jump near if carry (CF=1)
0F 84 cw/cd		JE rel16/32				Jump near if equal (ZF=1)
0F 84 cw/cd		JZ rel16/32				Jump near if 0 (ZF=1)
0F 8F cw/cd		JG rel16/32				Jump near if greater (ZF=0 and 
0F 8D cw/cd		JGE rel16/32			Jump near if greater or equal 
0F 8C cw/cd		JL rel16/32				Jump near if less (SFOF)
0F 8E cw/cd		JLE rel16/32			Jump near if less or equal (ZF=1 
0F 86 cw/cd		JNA rel16/32			Jump near if not above (CF=1 or 
0F 82 cw/cd		JNAE rel16/32			Jump near if not above or equal 
0F 83 cw/cd		JNB rel16/32			Jump near if not below (CF=0)
0F 87 cw/cd		JNBE rel16/32			Jump near if not below or equal 
0F 83 cw/cd		JNC rel16/32			Jump near if not carry (CF=0)
0F 85 cw/cd		JNE rel16/32			Jump near if not equal (ZF=0)
0F 8E cw/cd		JNG rel16/32			Jump near if not greater (ZF=1 
0F 8C cw/cd		JNGE rel16/32			Jump near if not greater or 
0F 8D cw/cd		JNL rel16/32			Jump near if not less (SF=OF)
0F 8F cw/cd		JNLE rel16/32			Jump near if not less or equal 
0F 81 cw/cd		JNO rel16/32			Jump near if not overflow (OF=0)
0F 8B cw/cd		JNP rel16/32			Jump near if not parity (PF=0)
0F 89 cw/cd		JNS rel16/32			Jump near if not sign (SF=0)
0F 85 cw/cd		JNZ rel16/32			Jump near if not zero (ZF=0)
0F 80 cw/cd		JO rel16/32				Jump near if overflow (OF=1)
0F 8A cw/cd		JP rel16/32				Jump near if parity (PF=1)
0F 8A cw/cd		JPE rel16/32			Jump near if parity even (PF=1)
0F 8B cw/cd		JPO rel16/32			Jump near if parity odd (PF=0)
0F 88 cw/cd		JS rel16/32				Jump near if sign (SF=1)
0F 84 cw/cd		JZ rel16/32				Jump near if 0 (ZF=1)
EB cb			JMP rel8				Jump short
E9 cw			JMP rel16				Jump near, displacement relative 
FF /4			JMP r/m16				Jump near indirect
EA cd			JMP ptr16:16			Jump intersegment, 4-byte 
EA cd			JMP ptr16:16			Jump to call gate, same 
EA cd			JMP ptr16:16			Jump via task state segment
EA cd			JMP ptr16:16			Jump via task gate
FF /5			JMP m16:16				Jump r/m16:16 indirect and 
FF /5			JMP m16:16				Jump to call gate, same 
FF /5			JMP m16:16				Jump via task state segment
FF /5			JMP m16:16				Jump via task gate
E9 cd			JMP rel32				Jump near, displacement relative 
FF /4			JMP r/m32				Jump near, indirect
EA cp			JMP ptr16:32			Jump intersegment, 6-byte 
EA cp			JMP ptr16:32			Jump to call gate, same 
EA cp			JMP ptr16:32			Jump via task state segment
EA cp			JMP ptr16:32			Jump via task gate
FF /5			JMP m16:32				Jump intersegment, address at 
FF /5			JMP m16:32				Jump to call gate, same 
FF /5			JMP m16:32				Jump via task state segment
FF /5			JMP m16:32				Jump via task gate
9F				LAHF					Load: AH = flags SF ZF xx AF xx PF xx CF
0F 02 /r		LAR r16,r/m16			r16 <- r/m16 masked by FF00
0F 02 /r		LAR r32,r/m32			r32 <- r/m32 masked by 00FxFF00
8D /r			LEA r16,m				Store effective address for m in register r16
8D /r			LEA r32,m				Store effective address for m in register r32
8D /r			LEA r16,m				Store effective address for m in register r16
8D /r			LEA r32,m				Store effective address for m in register r32
C9				LEAVE					Set SP to BP, then pop BP
C9				LEAVE					Set ESP to EBP, then pop EBP
0F 01 /2		LGDT m16&32				Load m into GDTR
0F 01 /3		LIDT m16&32				Load m into IDTR
C5 /r			LDS r16,m16:16			Load DS:r16 with pointer from memory
C5 /r			LDS r32,m16:32			Load DS:r32 with pointer from memory
0F B2 /r		LSS r16,m16:16			Load SS:r16 with pointer from memory
0F B2 /r		LSS r32,m16:32			Load SS:r32 with pointer from memory
C4 /r			LES r16,m16:16			Load ES:r16 with pointer from memory
C4 /r			LES r32,m16:32			Load ES:r32 with pointer from memory
0F B4 /r		LFS r16,m16:16			Load FS:r16 with pointer from memory
0F B4 /r		LFS r32,m16:32			Load FS:r32 with pointer from memory
0F B5 /r		LGS r16,m16:16			Load GS:r16 with pointer from memory
0F B5 /r		LGS r32,m16:32			Load GS:r32 with pointer from memory
0F 00 /2		LLDT r/m16				Load selector r/m16 into LDTR
0F 01 /6		LMSW r/m16				Load r/m16 in machine status word
F0				LOCK					Assert LOCK# signal for the next instruction
AC				LODS m8					Load byte [(E)SI] into AL
AD				LODS m16				Load word [(E)SI] into AX
AD				LODS m32				Load dword [(E)SI] into EAX
AC				LODSB					Load byte DS:[(E)SI] into AL
AD				LODSW					Load word DS:[(E)SI] into AX
AD				LODSD					Load dword DS:[(E)SI] into EAX
E2 cb			LOOP rel8				DEC count; jump short if count 0
E1 cb			LOOPE rel8				DEC count; jump short if count 0 and ZF=1
E1 cb			LOOPZ rel8				DEC count; jump short if count 0 and ZF=1
E0 cb			LOOPNE rel8				DEC count; jump short if count 0 and ZF=0
E0 cb			LOOPNZ rel8				DEC count; jump short if count 0 and ZF=0
0F 03 /r		LSL r16,r/m16			Load: r16 <- segment limit, 
0F 03 /r		LSL r32,r/m32			Load: r32 <- segment limit, 
0F 03 /r		LSL r16,r/m16			Load: r16 <- segment limit, 
0F 03 /r		LSL r32,r/m32			Load: r32 <- segment limit, 
88 /r			MOV r/m8,r8				Move byte register to r/m byte
89 /r			MOV r/m16,r16			Move word register to r/m word
89 /r			MOV r/m32,r32			Move dword register to r/m dword
8A /r			MOV r8,r/m8				Move r/m byte to byte register
8B /r			MOV r16,r/m16			Move r/m word to word register
8B /r			MOV r32,r/m32			Move r/m dword to dword register
8C /r			MOV r/m16,Sreg			Move segment register to r/m word
8D /r			MOV Sreg,r/m16			Move r/m word to segment register
A0				MOV AL,moffs8			Move byte at (seg:offset) to AL
A1				MOV AX,moffs16			Move word at (seg:offset) to AX
A1				MOV EAX,moffs32			Move dword at (seg:offset) to EAX
A2				MOV moffs8,AL			Move AL to (seg:offset)
A3				MOV moffs16,AX			Move AX to (seg:offset)
A3				MOV moffs32,EAX			Move EAX to (seg:offset)
B0 +r			MOV reg8,imm8			Move immediate byte to register
B8 +r			MOV reg16,imm16			Move immediate word to register
B8 +r			MOV reg32,imm32			Move immediate dword to register
C6				MOV r/m8,imm8			Move immediate byte to r/m byte
C7				MOV r/m16,imm16			Move immediate word to r/m word
C7				MOV r/m32,imm32			Move immediate dword to r/m dword
0F 20 /r		MOV r32,CR0/CR2/CR3		Move (control register) to 
0F 22 /r		MOV CR0/CR2/CR3,r32		Move (register) to (control 
0F 21 /r		MOV r32,DR0-3			Move (debug register) to 
0F 21 /r		MOV r32,DR6/DR7			Move (debug register) to 
0F 23 /r		MOV DR0-3,r32			Move (register) to (debug 
0F 23 /r		MOV DR6/DR7,r32			Move (register) to (debug 
0F 24 /r		MOV r32,TR6/TR7			Move (test register) to 
0F 26 /r		MOV TR6/TR7,r32			Move (register) to (test 
A4				MOVS m8,m8				Move byte [(E)SI] to ES:[(E)DI]
A5				MOVS m16,m16			Move word [(E)SI] to ES:[(E)DI]
A5				MOVS m32,m32			Move dword [(E)SI] to ES:[(E)DI]
A4				MOVSB					Move byte DS:[(E)SI] to ES:[(E)DI]
A5				MOVSW					Move word DS:[(E)SI] to ES:[(E)DI]
A5				MOVSD					Move dword DS:[(E)SI] to ES:[(E)DI]
0F BE /r		MOVSX r16,r/m8			Move byte to word with sign-extend
0F BE /r		MOVSX r32,r/m8			Move byte to dword, sign-extend
0F BF /r		MOVSX r32,r/m16			Move word to dword, sign-extend
0F B6 /r		MOVZX r16,r/m8			Move byte to word with zero-extend
0F B6 /r		MOVZX r32,r/m8			Move byte to dword, zero-extend
0F B7 /r		MOVZX r32,r/m16			Move word to dword, zero-extend
F6 /4			MUL AL,r/m8				Unsigned multiply (AX <- AL * r/m byte)
F7 /4			MUL AX,r/m16			Unsigned multiply (DX:AX <- AX * r/m 
F7 /4			MUL EAX,r/m32			Unsigned multiply (EDX:EAX <- EAX * r/m 
F6 /3			NEG r/m8				Two's complement negate r/m byte
F7 /3			NEG r/m16				Two's complement negate r/m word
F7 /3			NEG r/m32				Two's complement negate r/m dword
90				NOP						No operation
F6 /2			NOT r/m8				Reverse each bit of r/m byte
F7 /2			NOT r/m16				Reverse each bit of r/m word
F7 /2			NOT r/m32				Reverse each bit of r/m dword
0C ib			OR AL,imm8				OR immediate byte to AL
0D iw			OR AX,imm16				OR immediate word to AX
0D id			OR EAX,imm32			OR immediate dword to EAX
80 /1 ib		OR r/m8,imm8			OR immediate byte to r/m byte
81 /1 iw		OR r/m16,imm16			OR immediate word to r/m word
81 /1 id		OR r/m32,imm32			OR immediate dword to r/m dword
83 /1 ib		OR r/m16,imm8			OR sign-extended immediate byte 
83 /1 ib		OR r/m32,imm8			OR sign-extended immediate byte 
08 /r			OR r/m8,r8				OR byte register to r/m byte
09 /r			OR r/m16,r16			OR word register to r/m word
09 /r			OR r/m32,r32			OR dword register to r/m dword
0A /r			OR r8,r/m8				OR byte register to r/m byte
0B /r			OR r16,r/m16			OR word register to r/m word
0B /r			OR r32,r/m32			OR dword register to r/m dword
E6 ib			OUT imm8,AL				Output byte AL to immediate port 
E7 ib			OUT imm8,AX				Output word AL to immediate port 
E7 ib			OUT imm8,EAX			Output dword AL to immediate 
EE				OUT DX,AL				Output byte AL to port number in DX
EF				OUT DX,AX				Output word AL to port number in DX
EF				OUT DX,EAX				Output dword AL to port number 
6E				OUTS DX,r/m8			Output byte [(E)SI] to port in DX
6F				OUTS DX,r/m16			Output word [(E)SI] to port in DX
6F				OUTS DX,r/m32			Output dword [(E)SI] to port in DX
6E				OUTSB					Output byte DS:[(E)SI] to port in 
6F				OUTSW					Output word DS:[(E)SI] to port in 
6F				OUTSD					Output dword DS:[(E)SI] to port in 
8F /0			POP m16					Pop top of stack into memory word
8F /0			POP m32					Pop top of stack into memory dword
58 +r			POP r16					Pop top of stack into word register
58 +r			POP r32					Pop top of stack into dword register
1F				POP DS					Pop top of stack into DS
07				POP ES					Pop top of stack into ES
17				POP SS					Pop top of stack into SS
0F A1			POP FS					Pop top of stack into FS
0F A9			POP GS					Pop top of stack into GS
61				POPA					Pop DI, SI, BP, SP, BX, DX, CX, and AX
61				POPAD					Pop EDI, ESI, EBP, ESP, EDX, ECX, and EAX
9D				POPF					Pop top of stack FLAGS
9D				POPFD					Pop top of stack into EFLAGS
FF /6			PUSH m16				Push memory word
FF /6			PUSH m32				Push memory dword
50 +r			PUSH r16				Push register word
50 +r			PUSH r32				Push register dword
6A				PUSH imm8				Push immediate byte
68				PUSH imm16				Push immediate word
68				PUSH imm32				Push immediate dword
0E				PUSH CS					Push CS
16				PUSH SS					Push SS
1E				PUSH DS					Push DS
06				PUSH ES					Push ES
0F A0			PUSH FS					Push FS
0F A8			PUSH GS					Push GS
60				PUSHA					Push AX, CX, DX, BX, original SP, BP, SI, and DI
60				PUSHAD					Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI
9C				PUSHF					Push FLAGS
9C				PUSHFD					Push EFLAGS
D0 /2			RCL r/m8,1				Rotate 9 bits (CF,r/m byte) left 
D2 /2			RCL r/m8,CL				Rotate 9 bits (CF,r/m byte) left CL 
C0 /2 ib		RCL r/m8,imm8			Rotate 9 bits (CF,r/m byte) left 
D1 /2			RCL r/m16,1				Rotate 17 bits (CF,r/m word) left 
D3 /2			RCL r/m16,CL			Rotate 17 bits (CF,r/m word) left 
C1 /2 ib		RCL r/m16,imm8			Rotate 17 bits (CF,r/m word) left 
D1 /2			RCL r/m32,1				Rotate 33 bits (CF,r/m dword) left 
D3 /2			RCL r/m32,CL			Rotate 33 bits (CF,r/m dword) left 
C1 /2 ib		RCL r/m32,imm8			Rotate 33 bits (CF,r/m dword) left 
D0 /3			RCR r/m8,1				Rotate 9 bits (CF,r/m byte) right 
D2 /3			RCR r/m8,CL				Rotate 9 bits (CF,r/m byte) right 
C0 /3 ib		RCR r/m8,imm8			Rotate 9 bits (CF,r/m byte) right 
D1 /3			RCR r/m16,1				Rotate 17 bits (CF,r/m word) right 
D3 /3			RCR r/m16,CL			Rotate 17 bits (CF,r/m word) right 
C1 /3 ib		RCR r/m16,imm8			Rotate 17 bits (CF,r/m word) right 
D1 /3			RCR r/m32,1				Rotate 33 bits (CF,r/m dword) right 
D3 /3			RCR r/m32,CL			Rotate 33 bits (CF,r/m dword) right 
C1 /3 ib		RCR r/m32,imm8			Rotate 33 bits (CF,r/m dword) right 
D0 /0			ROL r/m8,1				Rotate 8 bits r/m byte left once
D2 /0			ROL r/m8,CL				Rotate 8 bits r/m byte left CL 
C0 /0 ib		ROL r/m8,imm8			Rotate 8 bits r/m byte left imm8 
D1 /0			ROL r/m16,1				Rotate 16 bits r/m word left once
D3 /0			ROL r/m16,CL			Rotate 16 bits r/m word left CL 
C1 /0 ib		ROL r/m16,imm8			Rotate 16 bits r/m word left imm8 
D1 /0			ROL r/m32,1				Rotate 32 bits r/m dword left once
D3 /0			ROL r/m32,CL			Rotate 32 bits r/m dword left CL 
C1 /0 ib		ROL r/m32,imm8			Rotate 32 bits r/m dword left imm8 
D0 /1			ROR r/m8,1				Rotate 8 bits r/m byte right once
D2 /1			ROR r/m8,CL				Rotate 8 bits r/m byte right CL 
C0 /1 ib		ROR r/m8,imm8			Rotate 8 bits r/m word right imm8 
D1 /1			ROR r/m16,1				Rotate 16 bits r/m word right once
D3 /1			ROR r/m16,CL			Rotate 16 bits r/m word right CL 
C1 /1 ib		ROR r/m16,imm8			Rotate 16 bits r/m word right imm8 
D1 /1			ROR r/m32,1				Rotate 32 bits r/m dword right once
D3 /1			ROR r/m32,CL			Rotate 32 bits r/m dword right CL 
C1 /1 ib		ROR r/m32,imm8			Rotate 32 bits r/m dword right imm8 
F3 6C			REP INS r/m8, DX		Input (E)CX bytes from port DX into ES:[(E)DI]
F3 6D			REP INS r/m16,DX		Input (E)CX words from port DX into ES:[(E)DI]
F3 6D			REP INS r/m32,DX		Input (E)CX dwords from port 
F3 A4			REP MOVS m8,m8			Move (E)CX bytes from 
F3 A5			REP MOVS m16,m16		Move (E)CX words from 
F3 A5			REP MOVS m32,m32		Move (E)CX dwords from 
F3 6E			REP OUTS DX,r/m8		Output (E)CX bytes from 
F3 6F			REP OUTS DX,r/m16		Output (E)CX words from 
F3 6F			REP OUTS DX,r/m32		Output (E)CX dwords from 
F3 AA			REP STOS m8				Fill (E)CX bytes at 
F3 AB			REP STOS m16			Fill (E)CX words at 
F3 AB			REP STOS m32			Fill (E)CX dwords at 
F3 A6			REPE CMPS m8,m8			Find nonmatching bytes in 
F3 A7			REPE CMPS m16,m16		Find nonmatching words in 
F3 A7			REPE CMPS m32,m32		Find nonmatching dwords in 
F3 AE			REPE SCAS m8			Find non-AL byte starting 
F3 AF			REPE SCAS m16			Find non-AX word starting 
F3 AF			REPE SCAS m32			Find non-EAX dword starting 
F2 A6			REPNE CMPS m8,m8		Find matching bytes in 
F2 A7			REPNE CMPS m16,m16		Find matching words in 
F2 A7			REPNE CMPS m32,m32		Find matching dwords in 
F2 AE			REPNE SCAS m8			Find AL, starting at 
F2 AF			REPNE SCAS m16			Find AX, starting at 
F2 AF			REPNE SCAS m32			Find EAX, starting at 
C3				RET						Return (near) to caller
CB				RET						Return (far) to caller, same 
CB				RET						Return (far), lesser privilege, 
C2 iw			RET imm16				Return (near), pop imm16 bytes of 
CA iw			RET imm16				Return (far), same privilege, pop 
CA iw			RET imm16				Return (far), lesser privilege, pop 
9E				SAHF					Store AH into flags SF ZF xx AF xx PF xx CF
D0 /4			SAL r/m8,1				Multiply r/m byte by 2, once
D2 /4			SAL r/m8,CL				Multiply r/m byte by 2, CL times
C0 /4 ib		SAL r/m8,imm8			Multiply r/m byte by 2, imm8 
D1 /4			SAL r/m16,1				Multiply r/m word by 2, once
D3 /4			SAL r/m16,CL			Multiply r/m word by 2, CL times
C1 /4 ib		SAL r/m16,imm8			Multiply r/m word by 2, imm8 
D1 /4			SAL r/m32,1				Multiply r/m dword by 2, once
D3 /4			SAL r/m32,CL			Multiply r/m dword by 2, CL 
C1 /4 ib		SAL r/m32,imm8			Multiply r/m dword by 2, imm8 
D0 /7			SAR r/m8,1				Signed divide^(1) r/m byte by 2, 
D2 /7			SAR r/m8,CL				Signed divide^(1) r/m byte by 2, 
C0 /7 ib		SAR r/m8,imm8			Signed divide^(1) r/m byte by 2, 
D1 /7			SAR r/m16,1				Signed divide^(1) r/m word by 2, 
D3 /7			SAR r/m16,CL			Signed divide^(1) r/m word by 2, 
C1 /7 ib		SAR r/m16,imm8			Signed divide^(1) r/m word by 2, 
D1 /7			SAR r/m32,1				Signed divide^(1) r/m dword by 2, 
D3 /7			SAR r/m32,CL			Signed divide^(1) r/m dword by 2, 
C1 /7 ib		SAR r/m32,imm8			Signed divide^(1) r/m dword by 2, 
D0 /4			SHL r/m8,1				Multiply r/m byte by 2, once
D2 /4			SHL r/m8,CL				Multiply r/m byte by 2, CL times
C0 /4 ib		SHL r/m8,imm8			Multiply r/m byte by 2, imm8 
D1 /4			SHL r/m16,1				Multiply r/m word by 2, once
D3 /4			SHL r/m16,CL			Multiply r/m word by 2, CL times
C1 /4 ib		SHL r/m16,imm8			Multiply r/m word by 2, imm8 
D1 /4			SHL r/m32,1				Multiply r/m dword by 2, once
D3 /4			SHL r/m32,CL			Multiply r/m dword by 2, CL 
C1 /4 ib		SHL r/m32,imm8			Multiply r/m dword by 2, imm8 
D0 /5			SHR r/m8,1				Unsigned divide r/m byte by 2, 
D2 /5			SHR r/m8,CL				Unsigned divide r/m byte by 2, 
C0 /5 ib		SHR r/m8,imm8			Unsigned divide r/m byte by 2, 
D1 /5			SHR r/m16,1				Unsigned divide r/m word by 2, 
D3 /5			SHR r/m16,CL			Unsigned divide r/m word by 2, 
C1 /5 ib		SHR r/m16,imm8			Unsigned divide r/m word by 2, 
D1 /5			SHR r/m32,1				Unsigned divide r/m dword by 2, 
D3 /5			SHR r/m32,CL			Unsigned divide r/m dword by 2, 
C1 /5 ib		SHR r/m32,imm8			Unsigned divide r/m dword by 2, 
1C ib			SBB AL,imm8				Subtract with borrow immediate byte 
1D iw			SBB AX,imm16			Subtract with borrow immediate word 
1D id			SBB EAX,imm32			Subtract with borrow immediate 
80 /3 ib		SBB r/m8,imm8			Subtract with borrow immediate byte 
81 /3 iw		SBB r/m16,imm16			Subtract with borrow immediate word 
81 /3 id		SBB r/m32,imm32			Subtract with borrow immediate 
83 /3 ib		SBB r/m16,imm8			Subtract with borrow sign-extended 
83 /3 ib		SBB r/m32,imm8			Subtract with borrow sign-extended 
18 /r			SBB r/m8,r8				Subtract with borrow byte register 
19 /r			SBB r/m16,r16			Subtract with borrow word register 
19 /r			SBB r/m32,r32			Subtract with borrow dword register 
1A /r			SBB r8,r/m8				Subtract with borrow byte register 
1B /r			SBB r16,r/m16			Subtract with borrow word register 
1B /r			SBB r32,r/m32			Subtract with borrow dword register 
AE				SCAS m8					Compare bytes AL-ES:[DI], update (E)DI
AF				SCAS m16				Compare words AX-ES:[DI], update (E)DI
AF				SCAS m32				Compare dwords EAX-ES:[DI], update (E)DI
AE				SCASB					Compare bytes AL-ES:[DI], update (E)DI
AF				SCASW					Compare words AX-ES:[DI], update (E)DI
AF				SCASD					Compare dwords EAX-ES:[DI], update (E)DI
0F 97			SETA r/m8				Set byte if above (CF=0 and ZF=0)
0F 93			SETAE r/m8				Set byte if above or equal (CF=0)
0F 92			SETB r/m8				Set byte if below (CF=1)
0F 96			SETBE r/m8				Set byte if below or equal (CF=1 or (ZF=1)
0F 92			SETC r/m8				Set if carry (CF=1)
0F 94			SETE r/m8				Set byte if equal (ZF=1)
0F 9F			SETG r/m8				Set byte if greater (ZF=0 or SF=OF)
0F 9D			SETGE r/m8				Set byte if greater or equal (SF=OF)
0F 9C			SETL r/m8				Set byte if less (SFOF)
0F 9E			SETLE r/m8				Set byte if less or equal (ZF=1 and SFOF)
0F 96			SETNA r/m8				Set byte if not above (CF=1)
0F 92			SETNAE r/m8				Set byte if not above or equal (CF=1)
0F 93			SETNB r/m8				Set byte if not below (CF=0)
0F 97			SETNBE r/m8				Set byte if not below or equal (CF=0 and ZF=0)
0F 93			SETNC r/m8				Set byte if not carry (CF=0)
0F 95			SETNE r/m8				Set byte if not equal (ZF=0)
0F 9E			SETNG r/m8				Set byte if not greater (ZF=1 or SFOF)
0F 9C			SETNGE r/m8				Set if not greater or equal (SFOF)
0F 9D			SETNL r/m8				Set byte if not less (SF=OF)
0F 9F			SETNLE r/m8				Set byte if not less or equal (ZF=1 and SFOF)
0F 91			SETNO r/m8				Set byte if not overflow (OF=0)
0F 9B			SETNP r/m8				Set byte if not parity (PF=0)
0F 99			SETNS r/m8				Set byte if not sign (SF=0)
0F 95			SETNZ r/m8				Set byte if not zero (ZF=0)
0F 90			SETO r/m8				Set byte if overflow (OF=1)
0F 9A			SETP r/m8				Set byte if parity (PF=1)
0F 9A			SETPE r/m8				Set byte if parity even (PF=1)
0F 9B			SETPO r/m8				Set byte if parity odd (PF=0)
0F 98			SETS r/m8				Set byte if sign (SF=1)
0F 94			SETZ r/m8				Set byte if zero (ZF=1)
0F 01 /0		SGDT m					Store GDTR to m
0F 01 /1		SIDT m					Store IDTR to m
0F A4			SHLD r/m16,r16,imm8		r/m16 gets SHL of r/m16 concatenated 
0F A4			SHLD r/m32,r32,imm8		r/m32 gets SHL of r/m32 concatenated 
0F A5			SHLD r/m16,r16,CL		r/m16 gets SHL of r/m16 concatenated 
0F A5			SHLD r/m32,r32,CL		r/m32 gets SHL of r/m32 concatenated 
0F AC			SHRD r/m16,r16,imm8		r/m16 gets SHR of r/m16 concatenated 
0F AC			SHRD r/m32,r32,imm8		r/m32 gets SHR of r/m32 concatenated 
0F AD			SHRD r/m16,r16,CL		r/m16 gets SHR of r/m16 concatenated 
0F AD			SHRD r/m32,r32,CL		r/m32 gets SHR of r/m32 concatenated 
0F 00 /0		SLDT r/m16				Store LDTR to EA word
0F 01 /4		SMSW r/m16				Store machine status word to EA 
F9				STC						Set carry flag
FD				STD						Set direction flag so (E)SI and/or (E)DI decrement
F13				STI						Set interrupt flag; interrupts enabled at the end of the next instruction
AA				STOS m8					Store AL in byte ES:[(E)DI], update (E)DI
AB				STOS m16				Store AX in word ES:[(E)DI], update (E)DI
AB				STOS m32				Store EAX in dword ES:[(E)DI], update (E)DI
AA				STOSB					Store AL in byte ES:[(E)DI], update (E)DI
AB				STOSW					Store AX in word ES:[(E)DI], update (E)DI
AB				STOSD					Store EAX in dword ES:[(E)DI], update (E)DI
0F 00 /1		STR r/m16				Load EA word into task register
2C ib			SUB AL,imm8				Subtract immediate byte from AL
2D iw			SUB AX,imm16			Subtract immediate word from AX
2D id			SUB EAX,imm32			Subtract immediate dword from EAX
80 /5 ib		SUB r/m8,imm8			Subtract immediate byte from r/m byte
81 /5 iw		SUB r/m16,imm16			Subtract immediate word from r/m word
81 /5 id		SUB r/m32,imm32			Subtract immediate dword from r/m 
83 /5 ib		SUB r/m16,imm8			Subtract sign-extended immediate byte 
83 /5 ib		SUB r/m32,imm8			Subtract sign-extended immediate byte 
28 /r			SUB r/m8,r8				Subtract byte register from r/m byte
29 /r			SUB r/m16,r16			Subtract word register from r/m word
29 /r			SUB r/m32,r32			Subtract dword register from r/m 
2A /r			SUB r8,r/m8				Subtract byte register from r/m byte
2B /r			SUB r16,r/m16			Subtract word register from r/m word
2B /r			SUB r32,r/m32			Subtract dword register from r/m 
A8 ib			TEST AL,imm8			AND immediate byte with AL
A9 iw			TEST AX,imm16			AND immediate word with AX
A9 id			TEST EAX,imm32			AND immediate dword with EAX
F6 /0 ib		TEST r/m8,imm8			AND immediate byte with r/m byte
F7 /0 iw		TEST r/m16,imm16		AND immediate word with r/m word
F7 /0 id		TEST r/m32,imm32		AND immediate dword with r/m dword
84 /r			TEST r/m8,r8			AND byte register with r/m byte
85 /r			TEST r/m16,r16			AND word register with r/m word
85 /r			TEST r/m32,r32			AND dword register with r/m dword
0F 00 /4		VERR r/m16				Set ZF=1 if segment can be read, 
0F 00 /5		VERW r/m16				Set ZF=1 if segment can be written, 
9B				WAIT					Wait until BUSY pin is inactive (HIGH)
90 +r			XCHG AX,r16				Exchange word register with AX
90 +r			XCHG r16,AX				Exchange word register with AX
90 +r			XCHG EAX,r32			Exchange dword register with EAX
90 +r			XCHG r32,EAX			Exchange dword register with EAX
86 /r			XCHG r/m8,r8			Exchange byte register with EA byte
86 /r			XCHG r8,r/m8			Exchange byte register with EA byte
87 /r			XCHG r/m16,r16			Exchange word register with EA word
87 /r			XCHG r16,r/m16			Exchange word register with EA word
87 /r			XCHG r/m32,r32			Exchange dword register with EA dword
87 /r			XCHG r32,r/m32			Exchange dword register with EA dword
34 ib			XOR AL,imm8				Exclusive-OR immediate byte to AL
35 iw			XOR AX,imm16			Exclusive-OR immediate word to AX
35 id			XOR EAX,imm32			Exclusive-OR immediate dword to EAX
80 /6 ib		XOR r/m8,imm8			Exclusive-OR immediate byte to r/m 
81 /6 iw		XOR r/m16,imm16			Exclusive-OR immediate word to r/m 
81 /6 id		XOR r/m32,imm32			Exclusive-OR immediate dword to r/m 
83 /6 ib		XOR r/m16,imm8			XOR sign-extended immediate byte 
83 /6 ib		XOR r/m32,imm8			XOR sign-extended immediate byte 
30 /r			XOR r/m8,r8				Exclusive-OR byte register to r/m 
31 /r			XOR r/m16,r16			Exclusive-OR word register to r/m 
31 /r			XOR r/m32,r32			Exclusive-OR dword register to r/m 
32 /r			XOR r8,r/m8				Exclusive-OR byte register to r/m 
33 /r			XOR r16,r/m16			Exclusive-OR word register to r/m 
33 /r			XOR r32,r/m32			Exclusive-OR dword register to r/m 

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