Plan 9 from Bell Labs’s /usr/web/sources/extra/9hist/pc/io.h

Copyright © 2021 Plan 9 Foundation.
Distributed under the MIT License.
Download the Plan 9 distribution.


## diffname pc/io.h 1991/0703
## diff -e /dev/null /n/bootesdump/1991/0703/sys/src/9/safari/io.h
0a
/*
 *  interrupt levels
 */
enum {
	Clockvec=	8,
	Kbdvec=		9,
	Floppyvec=	14,
};

/*
 *  damned 8259, assume DOS sets it up for us
 */
enum {
	Intctlport=	0x20,	/* 8259 control port */
	Intctlmask=	0x21,	/* interrupt mask */

	Intenable=	0x20,	/* written to Intctlport, enables next int */
};

#define	INTENABLE	outb(Intctlport, Intenable)
.
## diffname pc/io.h 1991/0704
## diff -e /n/bootesdump/1991/0703/sys/src/9/safari/io.h /n/bootesdump/1991/0704/sys/src/9/safari/io.h
20c
/*
 *  8237 dma controllers
 */
enum
{
	/*
	 *  the byte registers for DMA0 are all one byte apart
	 */
	Dma0=		0x00,
	Dma0status=	Dma0+0x8,	/* status port */
	Dma0reset=	Dma0+0xD,	/* reset port */

	/*
	 *  the byte registers for DMA1 are all two bytes apart (why?)
	 */
	Dma1=		0xC0,
	Dma1status=	Dma1+2*0x8,	/* status port */
	Dma0reset=	Dma1+2*0xD,	/* reset port */
};
.
17c
	Timerlatch=	0x40,		/* latch count into Timericnt */
.
13,15c
enum
{
	Timerctl=	0x43,		/* control port */
	Timercnt=	0x40,		/* timer count port (outb count-1) */
	Timericnt=	0x41,		/* timer count input port */
.
11c
 *  8253 timer
.
8a
#define	INT0ENABLE	outb(Int0ctl, Intena)
#define	INT1ENABLE	outb(Int1ctl, Intena)
.
4,7c
enum
{
	Int0ctl=	0x20,		/* control port */
	Int0aux=	0x21,		/* everything else port */
	Int1ctl=	0xA0,		/* control port */
	Int1aux=	0xA1,		/* everything else port */

	Intena=		0x20,		/* written to Intctlport, enables next int */

	Int0vec=	17,		/* first interrupt vector used by the 8259 */
	Clockvec=	Int0vec+0,	/* clock interrupts */
	Kbdvec=		Int0vec+1,	/* keyboard interrupts */
.
2c
 *  8259 interrupt controllers
.
## diffname pc/io.h 1991/0705
## diff -e /n/bootesdump/1991/0704/sys/src/9/safari/io.h /n/bootesdump/1991/0705/sys/src/9/safari/io.h
49c
	Dma1reset=	Dma1+2*0xD,	/* reset port */
.
21,32d
## diffname pc/io.h 1991/0706
## diff -e /n/bootesdump/1991/0705/sys/src/9/safari/io.h /n/bootesdump/1991/0706/sys/src/9/safari/io.h
13c
	Int0vec=	16,		/* first interrupt vector used by the 8259 */
.
## diffname pc/io.h 1991/0709
## diff -e /n/bootesdump/1991/0706/sys/src/9/safari/io.h /n/bootesdump/1991/0709/sys/src/9/safari/io.h
17,18d
6,12d
2c
 *  programmable interrupt vectors (for the 8259)
.
## diffname pc/io.h 1991/0710
## diff -e /n/bootesdump/1991/0709/sys/src/9/safari/io.h /n/bootesdump/1991/0710/sys/src/9/safari/io.h
5a
	Faultvec=	14,		/* page fault */
.
## diffname pc/io.h 1991/0730
## diff -e /n/bootesdump/1991/0710/sys/src/9/safari/io.h /n/bootesdump/1991/0730/sys/src/9/safari/io.h
9a
	Mousevec=	Int0vec+12,	/* mouse interrupt */
.
## diffname pc/io.h 1991/0731
## diff -e /n/bootesdump/1991/0730/sys/src/9/safari/io.h /n/bootesdump/1991/0731/sys/src/9/safari/io.h
7,30c
	Int0vec=	16,		/* first 8259 */
	 Clockvec=	Int0vec+0,	/*  clock interrupts */
	 Kbdvec=	Int0vec+1,	/*  keyboard interrupts */
	 ComBvec=	Int0vec+3,	/*  inerrupt from uart b */
	 ComAvec=	Int0vec+4,	/*  inerrupt from uart a */
	 Floppyvec=	Int0vec+6,	/*  floppy interrupts */
	Int1vec=	Int0vec+8,	/* second 8259 */
	 Mousevec=	Int1vec+4,	/*  mouse interrupt */
	 Hardvec=	Int1vec+6,	/*  hard disk */
.
2c
 *  programmable interrupt vectors (for the 8259's)
.
## diffname pc/io.h 1991/0801
## diff -e /n/bootesdump/1991/0731/sys/src/9/safari/io.h /n/bootesdump/1991/0801/sys/src/9/safari/io.h
10,11c
	 Uart0vec=	Int0vec+3,	/*  inerrupt from uart b */
	 Uart1vec=	Int0vec+4,	/*  inerrupt from uart a */
.
## diffname pc/io.h 1991/0806
## diff -e /n/bootesdump/1991/0801/sys/src/9/safari/io.h /n/bootesdump/1991/0806/sys/src/9/safari/io.h
10,11c
	 Uart0vec=	Int0vec+3,	/*  serial line */
	 Uart1vec=	Int0vec+4,	/*  modem line */
.
## diffname pc/io.h 1991/0810
## diff -e /n/bootesdump/1991/0806/sys/src/9/safari/io.h /n/bootesdump/1991/0810/sys/src/9/safari/io.h
10,11c
	 Uart0vec=	Int0vec+4,	/*  serial line */
	 Uart1vec=	Int0vec+3,	/*  modem line */
.
## diffname pc/io.h 1991/0811
## diff -e /n/bootesdump/1991/0810/sys/src/9/safari/io.h /n/bootesdump/1991/0811/sys/src/9/safari/io.h
11a
	 Uart0vec=	Int0vec+4,	/*  serial line */
.
10d
## diffname pc/io.h 1991/0904
## diff -e /n/bootesdump/1991/0811/sys/src/9/safari/io.h /n/bootesdump/1991/0904/sys/src/9/safari/io.h
7c
	Int0vec=	24,		/* first 8259 */
.
## diffname pc/io.h 1991/0905
## diff -e /n/bootesdump/1991/0904/sys/src/9/safari/io.h /n/bootesdump/1991/0905/sys/src/9/safari/io.h
6a

.
5a
	Coprocvec=	7,		/* math coprocessor interrupt */
.
## diffname pc/io.h 1991/0906
## diff -e /n/bootesdump/1991/0905/sys/src/9/safari/io.h /n/bootesdump/1991/0906/sys/src/9/safari/io.h
6c
	Mathemuvec=	7,		/* math coprocessor emulation interrupt */
	Mathovervec=	9,		/* math coprocessor overrun interrupt */
	Matherrorvec=	9,		/* math coprocessor error interrupt */
.
## diffname pc/io.h 1991/0910
## diff -e /n/bootesdump/1991/0906/sys/src/9/safari/io.h /n/bootesdump/1991/0910/sys/src/9/safari/io.h
19a

	Syscallvec=	64,
.
## diffname pc/io.h 1991/0912
## diff -e /n/bootesdump/1991/0910/sys/src/9/safari/io.h /n/bootesdump/1991/0912/sys/src/9/safari/io.h
18a
	 Matherr2vec=	Int1vec+5,	/*  math coprocessor */
.
8c
	Matherr1vec=	16,		/* math coprocessor error interrupt */
.
## diffname pc/io.h 1991/1112
## diff -e /n/bootesdump/1991/0912/sys/src/9/safari/io.h /n/bootesdump/1991/1112/sys/src/9/safari/io.h
5a
	Bptvec=		3,		/* breakpoints */
.
## diffname pc/io.h 1991/1127
## diff -e /n/bootesdump/1991/1112/sys/src/9/safari/io.h /n/bootesdump/1991/1127/sys/src/9/safari/io.h
17a
	 Parallelvec=	Int0vec+7,	/*  parallel port interrupts */
.
## diffname pc/io.h 1992/0403
## diff -e /n/bootesdump/1991/1127/sys/src/9/safari/io.h /n/bootesdump/1992/0403/sys/src/9/safari/io.h
16a
	 Ethervec=	Int0vec+5,	/*  ethernet interrupt */
.
## diffname pc/io.h 1992/0904
## diff -e /n/bootesdump/1992/0808/sys/src/9/safari/io.h /n/bootesdump/1992/0904/sys/src/9/pc/io.h
20,23c
	Int1vec=	Int0vec+8,
	 Ethervec=	Int0vec+10,	/*  ethernet interrupt */
	 Mousevec=	Int0vec+12,	/*  mouse interrupt */
	 Matherr2vec=	Int0vec+13,	/*  math coprocessor */
	 Hardvec=	Int0vec+14,	/*  hard disk */
.
17d
## diffname pc/io.h 1992/0922
## diff -e /n/bootesdump/1992/0904/sys/src/9/pc/io.h /n/bootesdump/1992/0922/sys/src/9/pc/io.h
26a

typedef struct EtherHw EtherHw;
typedef struct EtherBuf EtherBuf;
typedef struct EtherType EtherType;
typedef struct EtherCtlr EtherCtlr;

struct EtherHw {
	int	(*reset)(EtherCtlr*);
	void	(*init)(EtherCtlr*);
	void	(*mode)(EtherCtlr*, int);
	void	(*online)(EtherCtlr*, int);
	void	(*receive)(EtherCtlr*);
	void	(*transmit)(EtherCtlr*);
	void	(*intr)(EtherCtlr*);
	void	(*tweak)(EtherCtlr*);
	int	addr;			/* interface address */
	uchar	*ram;			/* interface shared memory address */
	int	bt16;			/* true if a 16 bit interface */
	int	irq;			/* interrupt level */
	int	size;
	uchar	tstart;
	uchar	pstart;
	uchar	pstop;
};

struct EtherBuf {
	uchar	owner;
	uchar	busy;
	ushort	len;
	uchar	pkt[sizeof(Etherpkt)];
};

enum {
	Host		= 0,		/* buffer owned by host */
	Interface	= 1,		/* buffer owned by interface */

	NType		= 9,		/* types/interface */
};

/*
 * one per ethernet packet type
 */
struct EtherType {
	QLock;
	Netprot;			/* stat info */
	int	type;			/* ethernet type */
	int	prom;			/* promiscuous mode */
	Queue	*q;
	int	inuse;
	EtherCtlr *ctlr;
};

/*
 * per ethernet
 */
struct EtherCtlr {
	QLock;

	EtherHw	*hw;
	int	present;

	ushort	nrb;		/* number of software receive buffers */
	ushort	ntb;		/* number of software transmit buffers */
	EtherBuf *rb;		/* software receive buffers */
	EtherBuf *tb;		/* software transmit buffers */

	uchar	ea[6];		/* ethernet address */
	uchar	ba[6];		/* broadcast address */

	Rendez	rr;		/* rendezvous for a receive buffer */
	ushort	rh;		/* first receive buffer belonging to host */
	ushort	ri;		/* first receive buffer belonging to interface */	

	Rendez	tr;		/* rendezvous for a transmit buffer */
	QLock	tlock;		/* semaphore on th */
	ushort	th;		/* first transmit buffer belonging to host */	
	ushort	ti;		/* first transmit buffer belonging to interface */	

	EtherType type[NType];
	uchar	prom;		/* true if promiscuous mode */
	uchar	kproc;		/* true if kproc started */
	char	name[NAMELEN];	/* name of kproc */
	Network	net;

	Queue	lbq;		/* software loopback packet queue */

	int	inpackets;
	int	outpackets;
	int	crcs;		/* input crc errors */
	int	oerrs;		/* output errors */
	int	frames;		/* framing errors */
	int	overflows;	/* packet overflows */
	int	buffs;		/* buffering errors */
};
.
## diffname pc/io.h 1992/0929
## diff -e /n/bootesdump/1992/0922/sys/src/9/pc/io.h /n/bootesdump/1992/0929/sys/src/9/pc/io.h
16a
	 PCMCIAvec=	Int0vec+5,	/*  PCMCIA card change */
.
## diffname pc/io.h 1992/1222
## diff -e /n/bootesdump/1992/0929/sys/src/9/pc/io.h /n/bootesdump/1992/1222/sys/src/9/pc/io.h
28,121d
## diffname pc/io.h 1994/0908
## diff -e /n/bootesdump/1992/1222/sys/src/9/pc/io.h /n/fornaxdump/1994/0908/sys/src/brazil/pc/io.h
26a
};

enum {
	MaxEISA		= 16,
.
24a
	 Vector15=	Int0vec+15,	/*  unassigned */
.
21c
	 Vector9=	Int0vec+9,	/*  unassigned */
	 Vector10=	Int0vec+10,	/*  unassigned, usually ethernet */
	 Vector11=	Int0vec+11,	/*  unassigned, usually scsi */
.
## diffname pc/io.h 1995/0126
## diff -e /n/fornaxdump/1994/0908/sys/src/brazil/pc/io.h /n/fornaxdump/1995/0126/sys/src/brazil/pc/io.h
33a
	EISAconfig	= 0xC80,
.
## diffname pc/io.h 1995/0517
## diff -e /n/fornaxdump/1995/0126/sys/src/brazil/pc/io.h /n/fornaxdump/1995/0517/sys/src/brazil/pc/io.h
35a

/*
 * PCI Local Bus support.
 * Quick hack until we figure out how to
 * deal with EISA, PCI, PCMCIA, PnP, etc.
 */
enum {					/* configuration mechanism #1 */
	PCIaddr		= 0xCF8,	/* CONFIG_ADDRESS */
	PCIdata		= 0xCFC,	/* CONFIG_DATA */

					/* configuration mechanism #2 */
	PCIcse		= 0xCF8,	/* configuration space enable */
	PCIforward	= 0xCFA,	/* which bus */
};

typedef struct PCIcfg {
	ushort	vid;			/* vendor ID */
	ushort	did;			/* device ID */
	ushort	command;	
	ushort	status;	
	uchar	rid;			/* revision ID */
	uchar	loclass;		/* specific register-level programming interface */
	uchar	subclass;	
	uchar	baseclass;	
	uchar	clsize;			/* cache line size */
	uchar	latency;		/* latency timer */
	uchar	header;			/* header type */
	uchar	bist;			/* built-in self-test */
	ulong	baseaddr[6];		/* memory or I/O base address registers */
	ulong	reserved28[2];	
	ulong	romaddr;		/* expansion ROM base address */
	ulong	reserved34[2];	
	uchar	irq;			/* interrupt line */
	uchar	irp;			/* interrupt pin */
	uchar	mingnt;			/* burst period length */
	uchar	maxlat;			/* maximum latency between bursts */
} PCIcfg;
.
## diffname pc/io.h 1995/0519
## diff -e /n/fornaxdump/1995/0517/sys/src/brazil/pc/io.h /n/fornaxdump/1995/0519/sys/src/brazil/pc/io.h
48a

	MaxPCI		= 16,
.
## diffname pc/io.h 1995/0726
## diff -e /n/fornaxdump/1995/0519/sys/src/brazil/pc/io.h /n/fornaxdump/1995/0726/sys/src/brazil/pc/io.h
49,50c
	
	MaxPCI		= 32,		/* 16 for mechanism #2 */
.
## diffname pc/io.h 1995/0818
## diff -e /n/fornaxdump/1995/0726/sys/src/brazil/pc/io.h /n/fornaxdump/1995/0818/sys/src/brazil/pc/io.h
26,27c
	 ATAvec0=	Int0vec+14,	/*  ATA controller #1 */
	 ATAvec1=	Int0vec+15,	/*  ATA controller #2 */
.
## diffname pc/io.h 1997/0327
## diff -e /n/fornaxdump/1995/0818/sys/src/brazil/pc/io.h /n/emeliedump/1997/0327/sys/src/brazil/pc/io.h
56,74c
	ulong	bar[2];			/* base address */
	uchar	intl;			/* interrupt line */

	Pcidev*	next;			/* next device on this bno */
} Pcidev;

/*
 * PCMCIA support code.
 */
/*
 * Map between ISA memory space and PCMCIA card memory space.
 */
struct PCMmap {
	ulong	ca;			/* card address */
	ulong	cea;			/* card end address */
	ulong	isa;			/* ISA address */
	int	len;			/* length of the ISA area */
	int	attr;			/* attribute memory */
	int	ref;
};
.
53c
enum {					/* type 0 pre-defined header */
	PciBAR2		= 0x18,
	PciBAR3		= 0x1C,
	PciBAR4		= 0x20,
	PciBAR5		= 0x24,
	PciCIS		= 0x28,		/* cardbus CIS pointer */
	PciSVID		= 0x2C,		/* subsystem vendor ID */
	PciSID		= 0x2E,		/* cardbus CIS pointer */
	PciEBAR0	= 0x30,		/* expansion ROM base address */
	PciMGNT		= 0x3E,		/* burst period length */
	PciMLT		= 0x3F,		/* maximum latency between bursts */
};

enum {					/* type 1 pre-defined header */
	PciPBN		= 0x18,		/* primary bus number */
	PciSBN		= 0x19,		/* secondary bus number */
	PciUBN		= 0x1A,		/* subordinate bus number */
	PciSLTR		= 0x1B,		/* secondary latency timer */
	PciIBR		= 0x1C,		/* I/O base */
	PciILR		= 0x1D,		/* I/O limit */
	PciSPSR		= 0x1E,		/* secondary status */
	PciMBR		= 0x20,		/* memory base */
	PciMLR		= 0x22,		/* memory limit */
	PciPMBR		= 0x24,		/* prefetchable memory base */
	PciPMLR		= 0x26,		/* prefetchable memory limit */
	PciPUBR		= 0x28,		/* prefetchable base upper 32 bits */
	PciPULR		= 0x2C,		/* prefetchable limit upper 32 bits */
	PciIUBR		= 0x30,		/* I/O base upper 16 bits */
	PciIULR		= 0x32,		/* I/O limit upper 16 bits */
	PciEBAR1	= 0x28,		/* expansion ROM base address */
	PciBCR		= 0x3E,		/* bridge control register */
};

typedef struct Pcidev Pcidev;
typedef struct Pcidev {
	int	tbdf;			/* type+bus+device+function */
.
46,50c
	PciBAR0		= 0x10,		/* base address */
	PciBAR1		= 0x14,

	PciINTL		= 0x3C,		/* interrupt line */
	PciINTP		= 0x3D,		/* interrupt pin */
.
42,44c
enum {					/* type 0 and type 1 pre-defined header */
	PciVID		= 0x00,		/* vendor ID */
	PciDID		= 0x02,		/* device ID */
	PciPCR		= 0x04,		/* command */
	PciPSR		= 0x06,		/* status */
	PciRID		= 0x08,		/* revision ID */
	PciCCRp		= 0x09,		/* programming interface class code */
	PciCCRu		= 0x0A,		/* sub-class code */
	PciCCRb		= 0x0B,		/* base class code */
	PciCLS		= 0x0C,		/* cache line size */
	PciLTR		= 0x0D,		/* latency timer */
	PciHDT		= 0x0E,		/* header type */
	PciBST		= 0x0F,		/* BIST */
.
38,40c
 * PCI support code.
.
32a
	BusCBUS		= 0,		/* Corollary CBUS */
	BusCBUSII,			/* Corollary CBUS II */
	BusEISA,			/* Extended ISA */
	BusFUTURE,			/* IEEE Futurebus */
	BusINTERN,			/* Internal bus */
	BusISA,				/* Industry Standard Architecture */
	BusMBI,				/* Multibus I */
	BusMBII,			/* Multibus II */
	BusMCA,				/* Micro Channel Architecture */
	BusMPI,				/* MPI */
	BusMPSA,			/* MPSA */
	BusNUBUS,			/* Apple Macintosh NuBus */
	BusPCI,				/* Peripheral Component Interconnect */
	BusPCMCIA,			/* PC Memory Card International Association */
	BusTC,				/* DEC TurboChannel */
	BusVL,				/* VESA Local bus */
	BusVME,				/* VMEbus */
	BusXPRESS,			/* Express System Bus */
};

#define MKBUS(t,b,d,f)	(((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
#define BUSFNO(tbdf)	(((tbdf)>>8)&0x07)
#define BUSDNO(tbdf)	(((tbdf)>>11)&0x1F)
#define BUSBNO(tbdf)	(((tbdf)>>16)&0xFF)
#define BUSTYPE(tbdf)	((tbdf)>>24)
#define BUSBDF(tbdf)	((tbdf)&0x00FFFF00)
#define BUSUNKNOWN	(-1)

enum {
.
29c
	VectorLAPIC	= 32,		/* local APIC interrupts */
	VectorLINT0	= VectorLAPIC+0,/* LINT[01] must be offsets 0 and 1 */
	VectorLINT1	= VectorLAPIC+1,
	VectorTIMER	= VectorLAPIC+2,
	VectorERROR	= VectorLAPIC+3,
	VectorPCINT	= VectorLAPIC+4,
	VectorSPURIOUS	= VectorLAPIC+15,/* must have bits [3-0] == 0x0F */
	MaxVectorLAPIC	= VectorLAPIC+15,

	VectorSYSCALL	= 64,

	VectorPIC	= 128,		/* external [A]PIC interrupts */
	VectorCLOCK	= VectorPIC+0,
	VectorKBD	= VectorPIC+1,
	VectorUART1	= VectorPIC+3,
	VectorUART0	= VectorPIC+4,
	VectorPCMCIA	= VectorPIC+5,
	VectorFLOPPY	= VectorPIC+6,
	VectorLPT	= VectorPIC+7,
	VectorIRQ7	= VectorPIC+7,
	VectorAUX	= VectorPIC+12,	/* PS/2 port */
	VectorIRQ13	= VectorPIC+13,	/* coprocessor on x386 */
	VectorATA0	= VectorPIC+14,
	MaxVectorPIC	= VectorPIC+15,
.
12,27c
enum {
	VectorBPT	= 3,		/* breakpoint */
	VectorCNA	= 7,		/* coprocessor not available */
	VectorCSO	= 9,		/* coprocessor segment overrun */
	VectorPF	= 14,		/* page fault */
	VectorCERR	= 16,		/* coprocessor error */
.
1,10c
#define X86STEPPING(x)	((x) & 0x0F)
#define X86MODEL(x)	(((x)>>4) & 0x0F)
#define X86FAMILY(x)	(((x)>>8) & 0x0F)
.
## diffname pc/io.h 1997/1011
## diff -e /n/emeliedump/1997/0327/sys/src/brazil/pc/io.h /n/emeliedump/1997/1011/sys/src/brazil/pc/io.h
137,138c

	Pcidev*	list;
	Pcidev*	bridge;			/* down a bus */
	Pcidev*	link;			/* next device on this bno */
};
.
135a
	ushort	ccru;
.
134c

	struct {
		ulong	bar;		/* base address */
		int	size;
	} mem[3];

.
## diffname pc/io.h 1998/0320
## diff -e /n/emeliedump/1997/1011/sys/src/brazil/pc/io.h /n/emeliedump/1998/0320/sys/src/brazil/pc/io.h
10a

	VectorINTR	= 32,		/* maskable interrupts */
.
5a
	VectorNMI	= 2,		/* non-maskable interrupt */
.
## diffname pc/io.h 1998/0910
## diff -e /n/emeliedump/1998/0320/sys/src/brazil/pc/io.h /n/emeliedump/1998/0910/sys/src/brazil/pc/io.h
165a

/*
 *  SCSI bus
 */
enum {
	MaxScsi		= 8,
	NTarget		= 8,		/* should be 16... */
};
struct Target {
	int	ctlrno;
	int	target;
	uchar*	inq;
	uchar*	scratch;

	Rendez	rendez;

	int	ok;
};

typedef int (*Scsiio)(Target*, int, uchar*, int, void*, int*);

typedef struct SCSIdev {
	char*	type;
	Scsiio	(*reset)(int, ISAConf*);
} SCSIdev;
.
40a
typedef struct Vctl {
	Vctl*	next;			/* handlers on this vector */

	int	isintr;			/* interrupt or fault/trap */
	int	irq;
	int	tbdf;
	int	(*isr)(int);		/* get isr bit for this irq */
	int	(*eoi)(int);		/* eoi */

	void	(*f)(Ureg*, void*);	/* handler to call */
	void*	a;			/* argument to call it with */
} Vctl;

.
26,38c
	VectorAPIC	= 65,		/* external APIC interrupts */
	MaxVectorAPIC	= 255,
.
15,22c
	VectorLAPIC	= VectorPIC+16,	/* local APIC interrupts */
	IrqLINT0	= 16,		/* LINT[01] must be offsets 0 and 1 */
	IrqLINT1	= 17,
	IrqTIMER	= 18,
	IrqERROR	= 19,
	IrqPCINT	= 20,
	IrqSPURIOUS	= 31,		/* must have bits [3-0] == 0x0F */
	MaxIrqLAPIC	= 31,
.
13c
	VectorPIC	= 32,		/* external i8259 interrupts */
	IrqCLOCK	= 0,
	IrqKBD		= 1,
	IrqUART1	= 3,
	IrqUART0	= 4,
	IrqPCMCIA	= 5,
	IrqFLOPPY	= 6,
	IrqLPT		= 7,
	IrqIRQ7		= 7,
	IrqAUX		= 12,		/* PS/2 port */
	IrqIRQ13	= 13,		/* coprocessor on 386 */
	IrqATA0		= 14,
	MaxIrqPIC	= 15,
.
## diffname pc/io.h 1998/1121
## diff -e /n/emeliedump/1998/0910/sys/src/brazil/pc/io.h /n/emeliedump/1998/1121/sys/src/brazil/pc/io.h
155c
	} mem[6];
.
## diffname pc/io.h 1999/0301
## diff -e /n/emeliedump/1998/1121/sys/src/brazil/pc/io.h /n/emeliedump/1999/0301/sys/src/brazil/pc/io.h
158,159c
	uchar	ccrp;
	uchar	ccru;
	uchar	ccrb;
.
147c
struct Pcidev
{
.
## diffname pc/io.h 1999/0622
## diff -e /n/emeliedump/1999/0301/sys/src/brazil/pc/io.h /n/emeliedump/1999/0622/sys/src/brazil/pc/io.h
165a

	Pcidev*	bridge;			/* down a bus */
	struct {
		ulong	bar;
		int	size;
	} ioa, mema;
.
164d
157a
	ulong	pcr;
.
145a
typedef struct Pcisiz Pcisiz;
struct Pcisiz
{
	Pcidev*	dev;
	int	siz;
	int	bar;
};

.
## diffname pc/io.h 1999/0713
## diff -e /n/emeliedump/1999/0622/sys/src/brazil/pc/io.h /n/emeliedump/1999/0713/sys/src/brazil/pc/io.h
220a

typedef struct SMBus SMBus;
struct SMBus {
	void	*arg;
	ulong	addr;
	int	(*quick)(SMBus*, int);
	int	(*send)(SMBus*, int, int);
	int	(*recv)(SMBus*, int, int*);
	int	(*bytewrite)(SMBus*, int);
	int	(*byteread)(SMBus*, int, int*);
	int	(*wordwrite)(SMBus*, int);
	int	(*wordread)(SMBus*, int, int*);
};
.
## diffname pc/io.h 1999/0715
## diff -e /n/emeliedump/1999/0713/sys/src/brazil/pc/io.h /n/emeliedump/1999/0715/sys/src/brazil/pc/io.h
224,232c
	QLock;		/* mutex */
	Rendez	r;	/* rendezvous point for completion interrupts */
	void	*arg;	/* implementation dependent */
	ulong	base;	/* port or memory base of smbus */
	int	busy;
	void	(*transact)(SMBus*, int, int, int, uchar*);
.
221a
/* SMBus transactions */
enum
{
	SMBquick,		/* sends address only */

	/* write */
	SMBsend,		/* sends address and cmd */
	SMBbytewrite,		/* sends address and cmd and 1 byte */
	SMBwordwrite,		/* sends address and cmd and 2 bytes */

	/* read */
	SMBrecv,		/* sends address, recvs 1 byte */
	SMBbyteread,		/* sends address and cmd, recv's byte */
	SMBwordread,		/* sends address and cmd, recv's 2 bytes */
};

.
## diffname pc/io.h 1999/0727
## diff -e /n/emeliedump/1999/0715/sys/src/brazil/pc/io.h /n/emeliedump/1999/0727/sys/src/brazil/pc/io.h
24a
	IrqATA1		= 15,
.
## diffname pc/io.h 1999/0819
## diff -e /n/emeliedump/1999/0727/sys/src/brazil/pc/io.h /n/emeliedump/1999/0819/sys/src/brazil/pc/io.h
45a
	char	name[NAMELEN];	/* of driver */
.
## diffname pc/io.h 1999/1007
## diff -e /n/emeliedump/1999/0819/sys/src/brazil/pc/io.h /n/emeliedump/1999/1007/sys/src/brazil/pc/io.h
7a
	VectorUD	= 6,		/* invalid opcode exception */
.
## diffname pc/io.h 2000/0405
## diff -e /n/emeliedump/1999/1007/sys/src/brazil/pc/io.h /n/emeliedump/2000/0405/sys/src/9/pc/io.h
47c
	char	name[NAMELEN];		/* of driver */
.
## diffname pc/io.h 2000/0506
## diff -e /n/emeliedump/2000/0405/sys/src/9/pc/io.h /n/emeliedump/2000/0506/sys/src/9/pc/io.h
199,223d
184a
#define PCIWINDOW	0
#define PCIWADDR(va)	(PADDR(va)+PCIWINDOW)
#define ISAWINDOW	0
#define ISAWADDR(va)	(PADDR(va)+ISAWINDOW)

.
182a
	ulong	pcr;
.
171,173d
169d
163a
	uchar	rid;
	uchar	ccrp;
	uchar	ccru;
	uchar	ccrb;

.
148a
enum {					/* type 2 pre-defined header */
	PciCBExCA	= 0x10,
	PciCBSPSR	= 0x16,
	PciCBPBN	= 0x18,		/* primary bus number */
	PciCBSBN	= 0x19,		/* secondary bus number */
	PciCBUBN	= 0x1A,		/* subordinate bus number */
	PciCBSLTR	= 0x1B,		/* secondary latency timer */
	PciCBMBR0	= 0x1C,
	PciCBMLR0	= 0x20,
	PciCBMBR1	= 0x24,
	PciCBMLR1	= 0x28,
	PciCBIBR0	= 0x2C,		/* I/O base */
	PciCBILR0	= 0x30,		/* I/O limit */
	PciCBIBR1	= 0x34,		/* I/O base */
	PciCBILR1	= 0x38,		/* I/O limit */
	PciCBSVID	= 0x40,		/* subsystem vendor ID */
	PciCBSID	= 0x42,		/* subsystem ID */
	PciCBLMBAR	= 0x44,		/* legacy mode base address */
};

.
89c
	CfgEISA		= 0xC80,
.
## diffname pc/io.h 2000/1118
## diff -e /n/emeliedump/2000/0506/sys/src/9/pc/io.h /n/emeliedump/2000/1118/sys/src/9/pc/io.h
250a
};

/*
 * PCMCIA support code.
 */

typedef struct PCMslot		PCMslot;
typedef struct PCMconftab	PCMconftab;
typedef struct Cisdat 		Cisdat;

/*
 * Map between ISA memory space and PCMCIA card memory space.
 */
struct PCMmap {
	ulong	ca;			/* card address */
	ulong	cea;			/* card end address */
	ulong	isa;			/* ISA address */
	int	len;			/* length of the ISA area */
	int	attr;			/* attribute memory */
	int	ref;
};

/* configuration table entry */
struct PCMconftab
{
	int	index;
	ushort	irqs;		/* legal irqs */
	uchar	irqtype;
	uchar	bit16;		/* true for 16 bit access */
	struct {
		ulong	start;
		ulong	len;
	} io[16];
	int	nio;
	uchar	vpp1;
	uchar	vpp2;
	uchar	memwait;
	ulong	maxwait;
	ulong	readywait;
	ulong	otherwait;
};

/* cis memory walking */
struct Cisdat
{
	uchar	*cisbase;
	int	cispos;
	int	cisskip;
	int	cislen;
};

/* a card slot */
struct PCMslot
{
	Lock;
	int	ref;

	void	*cp;		/* controller for this slot */
	long	memlen;		/* memory length */
	uchar	base;		/* index register base */
	uchar	slotno;		/* slot number */

	/* status */
	uchar	special;	/* in use for a special device */
	uchar	already;	/* already inited */
	uchar	occupied;
	uchar	battery;
	uchar	wrprot;
	uchar	powered;
	uchar	configed;
	uchar	enabled;
	uchar	busy;

	/* cis info */
	ulong	msec;		/* time of last slotinfo call */
	char	verstr[512];	/* version string */
	uchar	cpresent;	/* config registers present */
	ulong	caddr;		/* relative address of config registers */
	int	nctab;		/* number of config table entries */
	PCMconftab	ctab[8];
	PCMconftab	*def;		/* default conftab */

	/* for walking through cis */
	Cisdat;

	/* memory maps */
	Lock	mlock;		/* lock down the maps */
	int	time;
	PCMmap	mmap[4];	/* maps, last is always for the kernel */
.
212,226d
## diffname pc/io.h 2001/0527
## diff -e /n/emeliedump/2000/1118/sys/src/9/pc/io.h /n/emeliedump/2001/0527/sys/src/9/pc/io.h
47c
	char	name[KNAMELEN];		/* of driver */
.
## diffname pc/io.h 2001/0619
## diff -e /n/emeliedump/2001/0527/sys/src/9/pc/io.h /n/emeliedump/2001/0619/sys/src/9/pc/io.h
317,319d
278,286d
244d
## diffname pc/io.h 2001/0622
## diff -e /n/emeliedump/2001/0619/sys/src/9/pc/io.h /n/emeliedump/2001/0622/sys/src/9/pc/io.h
193a
	struct {
		ulong	bar;	
		int	size;
	} rom;
.

Bell Labs OSI certified Powered by Plan 9

(Return to Plan 9 Home Page)

Copyright © 2021 Plan 9 Foundation. All Rights Reserved.
Comments to webmaster@9p.io.