Plan 9 from Bell Labs’s /usr/web/sources/xen/xen2/9/xenpc/linuxbits.s

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Distributed under the MIT License.
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/* from linux -- find first set */
/* this should do BSFL	p+0(FP), EAX*/
#define BSFL BYTE $0xf; BYTE $0xbc; BYTE $0xc0
/*0FBCC0                bsfl %eax,%eax*/

TEXT ffs(SB), $0
	MOVL	v+0(FP), AX
	BSFL
	JNZ ffs_end
	MOVL	$-1, AX
ffs_end:	INCL	AX
	RET




#define LOCK  BYTE $0xF0; 
#define BTSLCX BYTE $0x0f; BYTE $0xAB; BYTE $0x1
#define BTCLCX BYTE $0x0f;  BYTE $0xBB; BYTE $0x01
#define BTRLCX BYTE $0x0f;	BYTE $0xB3; BYTE $0x01
#define BTLCX BYTE $0x0f; 	BYTE $0xA3; BYTE $0x01


	TEXT	synch_set_bit+0(SB),0,$20
	MOVL nr+0(FP), AX
	MOVL  p+4(FP), CX
	LOCK
	BTSLCX
	//BTSL		i+0(FP), p+4(FP)
	RET

	TEXT	synch_test_bit+0(SB),0,$20
	MOVL nr+0(FP), AX
	MOVL p+4(FP), CX
	BTLCX
	SBBL		AX, AX
	RET

	TEXT synch_test_and_set_bit+0(SB), 0,$20
	MOVL nr+0(FP), AX
	MOVL p+4(FP), CX
	LOCK
	BTSLCX
	SBBL		AX, AX
	RET

	TEXT synch_test_and_clear_bit+0(SB), 0,$20
	MOVL nr+0(FP), AX
	MOVL p+4(FP), CX
	LOCK
	BTRLCX
	SBBL		AX, AX
	RET


	TEXT	synch_clear_bit+0(SB),0,$20
	MOVL nr+0(FP), AX
	MOVL p+4(FP), CX
	LOCK
	BTRLCX
//	BTRL		i+0(FP), p+4(FP)
	RET

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